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1 /*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16 #ifndef NPCM7XX_H
17 #define NPCM7XX_H
18
19 #include "hw/boards.h"
20 #include "hw/cpu/a9mpcore.h"
21 #include "hw/gpio/npcm7xx_gpio.h"
22 #include "hw/mem/npcm7xx_mc.h"
23 #include "hw/misc/npcm7xx_clk.h"
24 #include "hw/misc/npcm7xx_gcr.h"
25 #include "hw/misc/npcm7xx_rng.h"
26 #include "hw/nvram/npcm7xx_otp.h"
27 #include "hw/timer/npcm7xx_timer.h"
28 #include "hw/ssi/npcm7xx_fiu.h"
29 #include "hw/usb/hcd-ehci.h"
30 #include "hw/usb/hcd-ohci.h"
31 #include "target/arm/cpu.h"
32
33 #define NPCM7XX_MAX_NUM_CPUS (2)
34
35 /* The first half of the address space is reserved for DDR4 DRAM. */
36 #define NPCM7XX_DRAM_BA (0x00000000)
37 #define NPCM7XX_DRAM_SZ (2 * GiB)
38
39 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
40 #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */
41 #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */
42 #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */
43 #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */
44 #define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */
45
46 typedef struct NPCM7xxMachine {
47 MachineState parent;
48 } NPCM7xxMachine;
49
50 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
51 #define NPCM7XX_MACHINE(obj) \
52 OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
53
54 typedef struct NPCM7xxMachineClass {
55 MachineClass parent;
56
57 const char *soc_type;
58 } NPCM7xxMachineClass;
59
60 #define NPCM7XX_MACHINE_CLASS(klass) \
61 OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE)
62 #define NPCM7XX_MACHINE_GET_CLASS(obj) \
63 OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
64
65 typedef struct NPCM7xxState {
66 DeviceState parent;
67
68 ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
69 A9MPPrivState a9mpcore;
70
71 MemoryRegion sram;
72 MemoryRegion irom;
73 MemoryRegion ram3;
74 MemoryRegion *dram;
75
76 NPCM7xxGCRState gcr;
77 NPCM7xxCLKState clk;
78 NPCM7xxTimerCtrlState tim[3];
79 NPCM7xxOTPState key_storage;
80 NPCM7xxOTPState fuse_array;
81 NPCM7xxMCState mc;
82 NPCM7xxRNGState rng;
83 NPCM7xxGPIOState gpio[8];
84 EHCISysBusState ehci;
85 OHCISysBusState ohci;
86 NPCM7xxFIUState fiu[2];
87 } NPCM7xxState;
88
89 #define TYPE_NPCM7XX "npcm7xx"
90 #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
91
92 #define TYPE_NPCM730 "npcm730"
93 #define TYPE_NPCM750 "npcm750"
94
95 typedef struct NPCM7xxClass {
96 DeviceClass parent;
97
98 /* Bitmask of modules that are permanently disabled on this chip. */
99 uint32_t disabled_modules;
100 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
101 uint32_t num_cpus;
102 } NPCM7xxClass;
103
104 #define NPCM7XX_CLASS(klass) \
105 OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
106 #define NPCM7XX_GET_CLASS(obj) \
107 OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
108
109 /**
110 * npcm7xx_load_kernel - Loads memory with everything needed to boot
111 * @machine - The machine containing the SoC to be booted.
112 * @soc - The SoC containing the CPU to be booted.
113 *
114 * This will set up the ARM boot info structure for the specific NPCM7xx
115 * derivative and call arm_load_kernel() to set up loading of the kernel, etc.
116 * into memory, if requested by the user.
117 */
118 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc);
119
120 #endif /* NPCM7XX_H */