2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GNU GPL v2.
13 #include "exec/memory.h"
14 #include "target/arm/cpu-qom.h"
15 #include "hw/pcmcia.h"
16 #include "qom/object.h"
18 /* Interrupt numbers */
19 # define PXA2XX_PIC_SSP3 0
20 # define PXA2XX_PIC_USBH2 2
21 # define PXA2XX_PIC_USBH1 3
22 # define PXA2XX_PIC_KEYPAD 4
23 # define PXA2XX_PIC_PWRI2C 6
24 # define PXA25X_PIC_HWUART 7
25 # define PXA27X_PIC_OST_4_11 7
26 # define PXA2XX_PIC_GPIO_0 8
27 # define PXA2XX_PIC_GPIO_1 9
28 # define PXA2XX_PIC_GPIO_X 10
29 # define PXA2XX_PIC_I2S 13
30 # define PXA26X_PIC_ASSP 15
31 # define PXA25X_PIC_NSSP 16
32 # define PXA27X_PIC_SSP2 16
33 # define PXA2XX_PIC_LCD 17
34 # define PXA2XX_PIC_I2C 18
35 # define PXA2XX_PIC_ICP 19
36 # define PXA2XX_PIC_STUART 20
37 # define PXA2XX_PIC_BTUART 21
38 # define PXA2XX_PIC_FFUART 22
39 # define PXA2XX_PIC_MMC 23
40 # define PXA2XX_PIC_SSP 24
41 # define PXA2XX_PIC_DMA 25
42 # define PXA2XX_PIC_OST_0 26
43 # define PXA2XX_PIC_RTC1HZ 30
44 # define PXA2XX_PIC_RTCALARM 31
47 # define PXA2XX_RX_RQ_I2S 2
48 # define PXA2XX_TX_RQ_I2S 3
49 # define PXA2XX_RX_RQ_BTUART 4
50 # define PXA2XX_TX_RQ_BTUART 5
51 # define PXA2XX_RX_RQ_FFUART 6
52 # define PXA2XX_TX_RQ_FFUART 7
53 # define PXA2XX_RX_RQ_SSP1 13
54 # define PXA2XX_TX_RQ_SSP1 14
55 # define PXA2XX_RX_RQ_SSP2 15
56 # define PXA2XX_TX_RQ_SSP2 16
57 # define PXA2XX_RX_RQ_ICP 17
58 # define PXA2XX_TX_RQ_ICP 18
59 # define PXA2XX_RX_RQ_STUART 19
60 # define PXA2XX_TX_RQ_STUART 20
61 # define PXA2XX_RX_RQ_MMCI 21
62 # define PXA2XX_TX_RQ_MMCI 22
63 # define PXA2XX_USB_RQ(x) ((x) + 24)
64 # define PXA2XX_RX_RQ_SSP3 66
65 # define PXA2XX_TX_RQ_SSP3 67
67 # define PXA2XX_SDRAM_BASE 0xa0000000
68 # define PXA2XX_INTERNAL_BASE 0x5c000000
69 # define PXA2XX_INTERNAL_SIZE 0x40000
72 DeviceState
*pxa2xx_pic_init(hwaddr base
, ARMCPU
*cpu
);
75 DeviceState
*pxa2xx_gpio_init(hwaddr base
,
76 ARMCPU
*cpu
, DeviceState
*pic
, int lines
);
77 void pxa2xx_gpio_read_notifier(DeviceState
*dev
, qemu_irq handler
);
80 DeviceState
*pxa255_dma_init(hwaddr base
, qemu_irq irq
);
81 DeviceState
*pxa27x_dma_init(hwaddr base
, qemu_irq irq
);
84 typedef struct PXA2xxLCDState PXA2xxLCDState
;
85 PXA2xxLCDState
*pxa2xx_lcdc_init(MemoryRegion
*sysmem
,
86 hwaddr base
, qemu_irq irq
);
87 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState
*s
, qemu_irq handler
);
90 #define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
91 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxMMCIState
, PXA2XX_MMCI
)
93 PXA2xxMMCIState
*pxa2xx_mmci_init(MemoryRegion
*sysmem
,
95 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
);
96 void pxa2xx_mmci_handlers(PXA2xxMMCIState
*s
, qemu_irq readonly
,
97 qemu_irq coverswitch
);
100 #define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
101 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState
, PXA2XX_PCMCIA
)
103 PXA2xxPCMCIAState
*pxa2xx_pcmcia_init(MemoryRegion
*sysmem
,
105 int pxa2xx_pcmcia_attach(void *opaque
, PCMCIACardState
*card
);
106 int pxa2xx_pcmcia_detach(void *opaque
);
107 void pxa2xx_pcmcia_set_irq_cb(void *opaque
, qemu_irq irq
, qemu_irq cd_irq
);
109 /* pxa2xx_keypad.c */
114 typedef struct PXA2xxKeyPadState PXA2xxKeyPadState
;
115 PXA2xxKeyPadState
*pxa27x_keypad_init(MemoryRegion
*sysmem
,
118 void pxa27x_register_keypad(PXA2xxKeyPadState
*kp
,
119 const struct keymap
*map
, int size
);
122 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
123 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState
, PXA2XX_I2C
)
125 PXA2xxI2CState
*pxa2xx_i2c_init(hwaddr base
,
126 qemu_irq irq
, uint32_t page_size
);
127 I2CBus
*pxa2xx_i2c_bus(PXA2xxI2CState
*s
);
129 typedef struct PXA2xxI2SState PXA2xxI2SState
;
131 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
132 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState
, PXA2XX_FIR
)
139 MemoryRegion internal
;
140 MemoryRegion cm_iomem
;
141 MemoryRegion mm_iomem
;
142 MemoryRegion pm_iomem
;
147 PXA2xxI2CState
*i2c
[2];
148 PXA2xxMMCIState
*mmc
;
149 PXA2xxPCMCIAState
*pcmcia
[2];
152 PXA2xxKeyPadState
*kp
;
154 /* Power management */
156 uint32_t pm_regs
[0x40];
158 /* Clock management */
163 /* Memory management */
165 uint32_t mm_regs
[0x1a];
167 /* Performance monitoring */
171 struct PXA2xxI2SState
{
176 void (*data_req
)(void *, int, int);
186 void (*codec_out
)(void *, uint32_t);
187 uint32_t (*codec_in
)(void *);
194 # define PA_FMT "0x%08lx"
196 PXA2xxState
*pxa270_init(unsigned int sdram_size
, const char *revision
);
197 PXA2xxState
*pxa255_init(unsigned int sdram_size
);