include/hw/arm/smmu-common.h

   1 /*
   2  * ARM SMMU Support
   3  *
   4  * Copyright (C) 2015-2016 Broadcom Corporation
   5  * Copyright (c) 2017 Red Hat, Inc.
   6  * Written by Prem Mallappa, Eric Auger
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #ifndef HW_ARM_SMMU_COMMON_H
  20 #define HW_ARM_SMMU_COMMON_H
  21
  22 #include "hw/sysbus.h"
  23 #include "hw/pci/pci.h"
  24 #include "qom/object.h"
  25
  26 #define SMMU_PCI_BUS_MAX      256
  27 #define SMMU_PCI_DEVFN_MAX    256
  28 #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
  29
  30 #define SMMU_MAX_VA_BITS      48
  31
  32 /*
  33  * Page table walk error types
  34  */
  35 typedef enum {
  36     SMMU_PTW_ERR_NONE,
  37     SMMU_PTW_ERR_WALK_EABT,   /* Translation walk external abort */
  38     SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
  39     SMMU_PTW_ERR_ADDR_SIZE,   /* Address Size fault */
  40     SMMU_PTW_ERR_ACCESS,      /* Access fault */
  41     SMMU_PTW_ERR_PERMISSION,  /* Permission fault */
  42 } SMMUPTWEventType;
  43
  44 typedef struct SMMUPTWEventInfo {
  45     SMMUPTWEventType type;
  46     dma_addr_t addr; /* fetched address that induced an abort, if any */
  47 } SMMUPTWEventInfo;
  48
  49 typedef struct SMMUTransTableInfo {
  50     bool disabled;             /* is the translation table disabled? */
  51     uint64_t ttb;              /* TT base address */
  52     uint8_t tsz;               /* input range, ie. 2^(64 -tsz)*/
  53     uint8_t granule_sz;        /* granule page shift */
  54     bool had;                  /* hierarchical attribute disable */
  55 } SMMUTransTableInfo;
  56
  57 typedef struct SMMUTLBEntry {
  58     IOMMUTLBEntry entry;
  59     uint8_t level;
  60     uint8_t granule;
  61 } SMMUTLBEntry;
  62
  63 /*
  64  * Generic structure populated by derived SMMU devices
  65  * after decoding the configuration information and used as
  66  * input to the page table walk
  67  */
  68 typedef struct SMMUTransCfg {
  69     int stage;                 /* translation stage */
  70     bool aa64;                 /* arch64 or aarch32 translation table */
  71     bool disabled;             /* smmu is disabled */
  72     bool bypassed;             /* translation is bypassed */
  73     bool aborted;              /* translation is aborted */
  74     uint64_t ttb;              /* TT base address */
  75     uint8_t oas;               /* output address width */
  76     uint8_t tbi;               /* Top Byte Ignore */
  77     uint16_t asid;
  78     SMMUTransTableInfo tt[2];
  79     uint32_t iotlb_hits;       /* counts IOTLB hits for this asid */
  80     uint32_t iotlb_misses;     /* counts IOTLB misses for this asid */
  81 } SMMUTransCfg;
  82
  83 typedef struct SMMUDevice {
  84     void               *smmu;
  85     PCIBus             *bus;
  86     int                devfn;
  87     IOMMUMemoryRegion  iommu;
  88     AddressSpace       as;
  89     uint32_t           cfg_cache_hits;
  90     uint32_t           cfg_cache_misses;
  91     QLIST_ENTRY(SMMUDevice) next;
  92 } SMMUDevice;
  93
  94 typedef struct SMMUPciBus {
  95     PCIBus       *bus;
  96     SMMUDevice   *pbdev[]; /* Parent array is sparse, so dynamically alloc */
  97 } SMMUPciBus;
  98
  99 typedef struct SMMUIOTLBKey {
 100     uint64_t iova;
 101     uint16_t asid;
 102     uint8_t tg;
 103     uint8_t level;
 104 } SMMUIOTLBKey;
 105
 106 struct SMMUState {
 107     /* <private> */
 108     SysBusDevice  dev;
 109     const char *mrtypename;
 110     MemoryRegion iomem;
 111
 112     GHashTable *smmu_pcibus_by_busptr;
 113     GHashTable *configs; /* cache for configuration data */
 114     GHashTable *iotlb;
 115     SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX];
 116     PCIBus *pci_bus;
 117     QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
 118     uint8_t bus_num;
 119     PCIBus *primary_bus;
 120 };
 121 typedef struct SMMUState SMMUState;
 122
 123 struct SMMUBaseClass {
 124     /* <private> */
 125     SysBusDeviceClass parent_class;
 126
 127     /*< public >*/
 128
 129     DeviceRealize parent_realize;
 130
 131 };
 132 typedef struct SMMUBaseClass SMMUBaseClass;
 133
 134 #define TYPE_ARM_SMMU "arm-smmu"
 135 DECLARE_OBJ_CHECKERS(SMMUState, SMMUBaseClass,
 136                      ARM_SMMU, TYPE_ARM_SMMU)
 137
 138 /* Return the SMMUPciBus handle associated to a PCI bus number */
 139 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
 140
 141 /* Return the stream ID of an SMMU device */
 142 static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
 143 {
 144     return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
 145 }
 146
 147 /**
 148  * smmu_ptw - Perform the page table walk for a given iova / access flags
 149  * pair, according to @cfg translation config
 150  */
 151 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
 152              SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
 153
 154 /**
 155  * select_tt - compute which translation table shall be used according to
 156  * the input iova and translation config and return the TT specific info
 157  */
 158 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
 159
 160 /* Return the iommu mr associated to @sid, or NULL if none */
 161 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
 162
 163 #define SMMU_IOTLB_MAX_SIZE 256
 164
 165 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
 166                                 SMMUTransTableInfo *tt, hwaddr iova);
 167 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
 168 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
 169                                 uint8_t tg, uint8_t level);
 170 void smmu_iotlb_inv_all(SMMUState *s);
 171 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
 172 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
 173                          uint8_t tg, uint64_t num_pages, uint8_t ttl);
 174
 175 /* Unmap the range of all the notifiers registered to any IOMMU mr */
 176 void smmu_inv_notifiers_all(SMMUState *s);
 177
 178 /* Unmap the range of all the notifiers registered to @mr */
 179 void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
 180
 181 #endif /* HW_ARM_SMMU_COMMON_H */