include/hw/arm/xlnx-zynqmp.h

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #ifndef XLNX_ZYNQMP_H
  19
  20 #include "qemu-common.h"
  21 #include "hw/arm/arm.h"
  22 #include "hw/intc/arm_gic.h"
  23 #include "hw/net/cadence_gem.h"
  24 #include "hw/char/cadence_uart.h"
  25 #include "hw/ide/pci.h"
  26 #include "hw/ide/ahci.h"
  27 #include "hw/sd/sdhci.h"
  28 #include "hw/ssi/xilinx_spips.h"
  29 #include "hw/dma/xlnx_dpdma.h"
  30 #include "hw/display/xlnx_dp.h"
  31
  32 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
  33 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
  34                                        TYPE_XLNX_ZYNQMP)
  35
  36 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
  37 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
  38 #define XLNX_ZYNQMP_NUM_GEMS 4
  39 #define XLNX_ZYNQMP_NUM_UARTS 2
  40 #define XLNX_ZYNQMP_NUM_SDHCI 2
  41 #define XLNX_ZYNQMP_NUM_SPIS 2
  42
  43 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
  44 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
  45 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
  46
  47 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
  48 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
  49 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
  50
  51 #define XLNX_ZYNQMP_GIC_REGIONS 2
  52
  53 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
  54  * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
  55  * aligned address in the 64k region. To implement each GIC region needs a
  56  * number of memory region aliases.
  57  */
  58
  59 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
  60 #define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
  61
  62 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
  63
  64 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
  65 #define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
  66
  67 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
  68                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
  69
  70 typedef struct XlnxZynqMPState {
  71     /*< private >*/
  72     DeviceState parent_obj;
  73
  74     /*< public >*/
  75     ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
  76     ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
  77     GICState gic;
  78     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
  79
  80     MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
  81
  82     MemoryRegion *ddr_ram;
  83     MemoryRegion ddr_ram_low, ddr_ram_high;
  84
  85     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
  86     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
  87     SysbusAHCIState sata;
  88     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
  89     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
  90     XlnxZynqMPQSPIPS qspi;
  91     XlnxDPState dp;
  92     XlnxDPDMAState dpdma;
  93
  94     char *boot_cpu;
  95     ARMCPU *boot_cpu_ptr;
  96
  97     /* Has the ARM Security extensions?  */
  98     bool secure;
  99     /* Has the ARM Virtualization extensions?  */
 100     bool virt;
 101     /* Has the RPU subsystem?  */
 102     bool has_rpu;
 103 }  XlnxZynqMPState;
 104
 105 #define XLNX_ZYNQMP_H
 106 #endif