4 * Copyright (c) 2020 Intel
6 * This work is licensed under the terms of the GNU GPL, version 2. See the
7 * COPYING file in the top-level directory.
13 #include "hw/cxl/cxl_component.h"
14 #include "hw/pci/pci_device.h"
15 #include "hw/register.h"
18 * The following is how a CXL device's Memory Device registers are laid out.
19 * The only requirement from the spec is that the capabilities array and the
20 * capability headers start at offset 0 and are contiguously packed. The headers
21 * themselves provide offsets to the register fields. For this emulation, the
22 * actual registers * will start at offset 0x80 (m == 0x80). No secondary
23 * mailbox is implemented which means that the offset of the start of the
24 * mailbox payload (n) is given by
25 * n = m + sizeof(mailbox registers) + sizeof(device registers).
27 * +---------------------------------+
29 * | Memory Device Registers |
31 * n + PAYLOAD_SIZE_MAX -----------------------------------
37 * | | Mailbox Payload |
41 * n -----------------------------------
42 * ^ | Mailbox Registers |
44 * | -----------------------------------
46 * | | Device Registers |
48 * m ---------------------------------->
49 * ^ | Memory Device Capability Header|
50 * | -----------------------------------
51 * | | Mailbox Capability Header |
52 * | -----------------------------------
53 * | | Device Capability Header |
54 * | -----------------------------------
55 * | | Device Cap Array Register |
56 * 0 +---------------------------------+
60 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */
61 #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */
62 #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */
63 #define CXL_CAPS_SIZE \
64 (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */
66 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */
67 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */
69 #define CXL_MAILBOX_REGISTERS_OFFSET \
70 (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH)
71 #define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */
72 #define CXL_MAILBOX_PAYLOAD_SHIFT 11
73 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT)
74 #define CXL_MAILBOX_REGISTERS_LENGTH \
75 (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE)
77 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \
78 (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH)
79 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8
81 #define CXL_MMIO_SIZE \
82 (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \
83 CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
85 typedef struct cxl_device_state
{
86 MemoryRegion device_registers
;
88 /* mmio for device capabilities array - 8.2.8.2 */
90 MemoryRegion memory_device
;
94 uint32_t caps_reg_state32
[CXL_CAPS_SIZE
/ 4];
95 uint64_t caps_reg_state64
[CXL_CAPS_SIZE
/ 8];
99 /* mmio for the mailbox registers 8.2.8.4 */
101 MemoryRegion mailbox
;
102 uint16_t payload_size
;
104 uint8_t mbox_reg_state
[CXL_MAILBOX_REGISTERS_LENGTH
];
105 uint16_t mbox_reg_state16
[CXL_MAILBOX_REGISTERS_LENGTH
/ 2];
106 uint32_t mbox_reg_state32
[CXL_MAILBOX_REGISTERS_LENGTH
/ 4];
107 uint64_t mbox_reg_state64
[CXL_MAILBOX_REGISTERS_LENGTH
/ 8];
122 /* memory region for persistent memory, HDM */
126 /* Initialize the register block for a device */
127 void cxl_device_register_block_init(Object
*obj
, CXLDeviceState
*dev
);
129 /* Set up default values for the register block */
130 void cxl_device_register_init_common(CXLDeviceState
*dev
);
133 * CXL 2.0 - 8.2.8.1 including errata F4
134 * Documented as a 128 bit register, but 64 bit accesses and the second
135 * 64 bits are currently reserved.
137 REG64(CXL_DEV_CAP_ARRAY
, 0) /* Documented as 128 bit register but 64 byte accesses */
138 FIELD(CXL_DEV_CAP_ARRAY
, CAP_ID
, 0, 16)
139 FIELD(CXL_DEV_CAP_ARRAY
, CAP_VERSION
, 16, 8)
140 FIELD(CXL_DEV_CAP_ARRAY
, CAP_COUNT
, 32, 16)
143 * Helper macro to initialize capability headers for CXL devices.
145 * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says:
146 * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
147 * > is the maximum access size allowed for these registers. If this rule is not
148 * > followed, the behavior is undefined
150 * CXL 2.0 Errata F4 states futher that the layouts in the specification are
151 * shown as greater than 128 bits, but implementations are expected to
152 * use any size of access up to 64 bits.
154 * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple
155 * access to be used for a register up to 64 bits.
157 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \
158 REG32(CXL_DEV_##n##_CAP_HDR0, offset) \
159 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \
160 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \
161 REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \
162 FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \
163 REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \
164 FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32)
166 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS
, CXL_DEVICE_CAP_HDR1_OFFSET
)
167 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX
, CXL_DEVICE_CAP_HDR1_OFFSET
+ \
168 CXL_DEVICE_CAP_REG_SIZE
)
169 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE
,
170 CXL_DEVICE_CAP_HDR1_OFFSET
+
171 CXL_DEVICE_CAP_REG_SIZE
* 2)
173 int cxl_initialize_mailbox(CXLDeviceState
*cxl_dstate
);
174 void cxl_process_mailbox(CXLDeviceState
*cxl_dstate
);
176 #define cxl_device_cap_init(dstate, reg, cap_id) \
178 uint32_t *cap_hdrs = dstate->caps_reg_state32; \
179 int which = R_CXL_DEV_##reg##_CAP_HDR0; \
181 FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \
183 cap_hdrs[which] = FIELD_DP32( \
184 cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \
185 cap_hdrs[which + 1] = \
186 FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \
187 CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \
188 cap_hdrs[which + 2] = \
189 FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \
190 CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \
193 /* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */
194 REG32(CXL_DEV_MAILBOX_CAP
, 0)
195 FIELD(CXL_DEV_MAILBOX_CAP
, PAYLOAD_SIZE
, 0, 5)
196 FIELD(CXL_DEV_MAILBOX_CAP
, INT_CAP
, 5, 1)
197 FIELD(CXL_DEV_MAILBOX_CAP
, BG_INT_CAP
, 6, 1)
198 FIELD(CXL_DEV_MAILBOX_CAP
, MSI_N
, 7, 4)
200 /* CXL 2.0 8.2.8.4.4 Mailbox Control Register */
201 REG32(CXL_DEV_MAILBOX_CTRL
, 4)
202 FIELD(CXL_DEV_MAILBOX_CTRL
, DOORBELL
, 0, 1)
203 FIELD(CXL_DEV_MAILBOX_CTRL
, INT_EN
, 1, 1)
204 FIELD(CXL_DEV_MAILBOX_CTRL
, BG_INT_EN
, 2, 1)
206 /* CXL 2.0 8.2.8.4.5 Command Register */
207 REG64(CXL_DEV_MAILBOX_CMD
, 8)
208 FIELD(CXL_DEV_MAILBOX_CMD
, COMMAND
, 0, 8)
209 FIELD(CXL_DEV_MAILBOX_CMD
, COMMAND_SET
, 8, 8)
210 FIELD(CXL_DEV_MAILBOX_CMD
, LENGTH
, 16, 20)
212 /* CXL 2.0 8.2.8.4.6 Mailbox Status Register */
213 REG64(CXL_DEV_MAILBOX_STS
, 0x10)
214 FIELD(CXL_DEV_MAILBOX_STS
, BG_OP
, 0, 1)
215 FIELD(CXL_DEV_MAILBOX_STS
, ERRNO
, 32, 16)
216 FIELD(CXL_DEV_MAILBOX_STS
, VENDOR_ERRNO
, 48, 16)
218 /* CXL 2.0 8.2.8.4.7 Background Command Status Register */
219 REG64(CXL_DEV_BG_CMD_STS
, 0x18)
220 FIELD(CXL_DEV_BG_CMD_STS
, OP
, 0, 16)
221 FIELD(CXL_DEV_BG_CMD_STS
, PERCENTAGE_COMP
, 16, 7)
222 FIELD(CXL_DEV_BG_CMD_STS
, RET_CODE
, 32, 16)
223 FIELD(CXL_DEV_BG_CMD_STS
, VENDOR_RET_CODE
, 48, 16)
225 /* CXL 2.0 8.2.8.4.8 Command Payload Registers */
226 REG32(CXL_DEV_CMD_PAYLOAD
, 0x20)
228 REG64(CXL_MEM_DEV_STS
, 0)
229 FIELD(CXL_MEM_DEV_STS
, FATAL
, 0, 1)
230 FIELD(CXL_MEM_DEV_STS
, FW_HALT
, 1, 1)
231 FIELD(CXL_MEM_DEV_STS
, MEDIA_STATUS
, 2, 2)
232 FIELD(CXL_MEM_DEV_STS
, MBOX_READY
, 4, 1)
233 FIELD(CXL_MEM_DEV_STS
, RESET_NEEDED
, 5, 3)
237 PCIDevice parent_obj
;
240 HostMemoryBackend
*hostmem
;
241 HostMemoryBackend
*lsa
;
245 AddressSpace hostmem_as
;
246 CXLComponentState cxl_cstate
;
247 CXLDeviceState cxl_dstate
;
253 #define TYPE_CXL_TYPE3 "cxl-type3"
254 OBJECT_DECLARE_TYPE(CXLType3Dev
, CXLType3Class
, CXL_TYPE3
)
256 struct CXLType3Class
{
258 PCIDeviceClass parent_class
;
261 uint64_t (*get_lsa_size
)(CXLType3Dev
*ct3d
);
263 uint64_t (*get_lsa
)(CXLType3Dev
*ct3d
, void *buf
, uint64_t size
,
265 void (*set_lsa
)(CXLType3Dev
*ct3d
, const void *buf
, uint64_t size
,
269 MemTxResult
cxl_type3_read(PCIDevice
*d
, hwaddr host_addr
, uint64_t *data
,
270 unsigned size
, MemTxAttrs attrs
);
271 MemTxResult
cxl_type3_write(PCIDevice
*d
, hwaddr host_addr
, uint64_t data
,
272 unsigned size
, MemTxAttrs attrs
);