include/hw/i386/apic_internal.h

   1 /*
   2  *  APIC support - internal interfaces
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #ifndef QEMU_APIC_INTERNAL_H
  21 #define QEMU_APIC_INTERNAL_H
  22
  23 #include "exec/memory.h"
  24 #include "hw/cpu/icc_bus.h"
  25 #include "qemu/timer.h"
  26
  27 /* APIC Local Vector Table */
  28 #define APIC_LVT_TIMER                  0
  29 #define APIC_LVT_THERMAL                1
  30 #define APIC_LVT_PERFORM                2
  31 #define APIC_LVT_LINT0                  3
  32 #define APIC_LVT_LINT1                  4
  33 #define APIC_LVT_ERROR                  5
  34 #define APIC_LVT_NB                     6
  35
  36 /* APIC delivery modes */
  37 #define APIC_DM_FIXED                   0
  38 #define APIC_DM_LOWPRI                  1
  39 #define APIC_DM_SMI                     2
  40 #define APIC_DM_NMI                     4
  41 #define APIC_DM_INIT                    5
  42 #define APIC_DM_SIPI                    6
  43 #define APIC_DM_EXTINT                  7
  44
  45 /* APIC destination mode */
  46 #define APIC_DESTMODE_FLAT              0xf
  47 #define APIC_DESTMODE_CLUSTER           1
  48
  49 #define APIC_TRIGGER_EDGE               0
  50 #define APIC_TRIGGER_LEVEL              1
  51
  52 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  53 #define APIC_LVT_MASKED                 (1<<16)
  54 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  55 #define APIC_LVT_REMOTE_IRR             (1<<14)
  56 #define APIC_INPUT_POLARITY             (1<<13)
  57 #define APIC_SEND_PENDING               (1<<12)
  58
  59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  60
  61 #define APIC_SV_DIRECTED_IO             (1<<12)
  62 #define APIC_SV_ENABLE                  (1<<8)
  63
  64 #define VAPIC_ENABLE_BIT                0
  65 #define VAPIC_ENABLE_MASK               (1 << VAPIC_ENABLE_BIT)
  66
  67 #define MAX_APICS 255
  68
  69 typedef struct APICCommonState APICCommonState;
  70
  71 #define TYPE_APIC_COMMON "apic-common"
  72 #define APIC_COMMON(obj) \
  73      OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC_COMMON)
  74 #define APIC_COMMON_CLASS(klass) \
  75      OBJECT_CLASS_CHECK(APICCommonClass, (klass), TYPE_APIC_COMMON)
  76 #define APIC_COMMON_GET_CLASS(obj) \
  77      OBJECT_GET_CLASS(APICCommonClass, (obj), TYPE_APIC_COMMON)
  78
  79 typedef struct APICCommonClass
  80 {
  81     ICCDeviceClass parent_class;
  82
  83     void (*init)(APICCommonState *s);
  84     void (*set_base)(APICCommonState *s, uint64_t val);
  85     void (*set_tpr)(APICCommonState *s, uint8_t val);
  86     uint8_t (*get_tpr)(APICCommonState *s);
  87     void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
  88     void (*vapic_base_update)(APICCommonState *s);
  89     void (*external_nmi)(APICCommonState *s);
  90     void (*pre_save)(APICCommonState *s);
  91     void (*post_load)(APICCommonState *s);
  92 } APICCommonClass;
  93
  94 struct APICCommonState {
  95     ICCDevice busdev;
  96
  97     MemoryRegion io_memory;
  98     X86CPU *cpu;
  99     uint32_t apicbase;
 100     uint8_t id;
 101     uint8_t arb_id;
 102     uint8_t tpr;
 103     uint32_t spurious_vec;
 104     uint8_t log_dest;
 105     uint8_t dest_mode;
 106     uint32_t isr[8];  /* in service register */
 107     uint32_t tmr[8];  /* trigger mode register */
 108     uint32_t irr[8]; /* interrupt request register */
 109     uint32_t lvt[APIC_LVT_NB];
 110     uint32_t esr; /* error register */
 111     uint32_t icr[2];
 112
 113     uint32_t divide_conf;
 114     int count_shift;
 115     uint32_t initial_count;
 116     int64_t initial_count_load_time;
 117     int64_t next_time;
 118     int idx;
 119     QEMUTimer *timer;
 120     int64_t timer_expiry;
 121     int sipi_vector;
 122     int wait_for_sipi;
 123
 124     uint32_t vapic_control;
 125     DeviceState *vapic;
 126     hwaddr vapic_paddr; /* note: persistence via kvmvapic */
 127 };
 128
 129 typedef struct VAPICState {
 130     uint8_t tpr;
 131     uint8_t isr;
 132     uint8_t zero;
 133     uint8_t irr;
 134     uint8_t enabled;
 135 } QEMU_PACKED VAPICState;
 136
 137 extern bool apic_report_tpr_access;
 138
 139 void apic_report_irq_delivered(int delivered);
 140 bool apic_next_timer(APICCommonState *s, int64_t current_time);
 141 void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
 142 void apic_enable_vapic(DeviceState *d, hwaddr paddr);
 143
 144 void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
 145                              TPRAccess access);
 146
 147 #endif /* !QEMU_APIC_INTERNAL_H */