include/hw/i386/ich9.h

   1 #ifndef HW_ICH9_H
   2 #define HW_ICH9_H
   3
   4 #include "hw/hw.h"
   5 #include "hw/isa/isa.h"
   6 #include "hw/sysbus.h"
   7 #include "hw/i386/pc.h"
   8 #include "hw/isa/apm.h"
   9 #include "hw/i386/ioapic.h"
  10 #include "hw/pci/pci.h"
  11 #include "hw/pci/pcie_host.h"
  12 #include "hw/pci/pci_bridge.h"
  13 #include "hw/acpi/acpi.h"
  14 #include "hw/acpi/ich9.h"
  15 #include "hw/pci/pci_bus.h"
  16
  17 void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
  18 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
  19 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
  20 void ich9_lpc_pm_init(PCIDevice *pci_lpc);
  21 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
  22
  23 #define ICH9_CC_SIZE                            (16 * 1024)     /* 16KB */
  24
  25 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
  26 #define ICH9_LPC_DEVICE(obj) \
  27      OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
  28
  29 typedef struct ICH9LPCState {
  30     /* ICH9 LPC PCI to ISA bridge */
  31     PCIDevice d;
  32
  33     /* (pci device, intx) -> pirq
  34      * In real chipset case, the unused slots are never used
  35      * as ICH9 supports only D25-D32 irq routing.
  36      * On the other hand in qemu case, any slot/function can be populated
  37      * via command line option.
  38      * So fallback interrupt routing for any devices in any slots is necessary.
  39     */
  40     uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
  41
  42     APMState apm;
  43     ICH9LPCPMRegs pm;
  44     uint32_t sci_level; /* track sci level */
  45
  46     /* 10.1 Chipset Configuration registers(Memory Space)
  47      which is pointed by RCBA */
  48     uint8_t chip_config[ICH9_CC_SIZE];
  49
  50     /*
  51      * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
  52      *
  53      * register contents and IO memory region
  54      */
  55     uint8_t rst_cnt;
  56     MemoryRegion rst_cnt_mem;
  57
  58     /* isa bus */
  59     ISABus *isa_bus;
  60     MemoryRegion rbca_mem;
  61     Notifier machine_ready;
  62
  63     qemu_irq *pic;
  64     qemu_irq *ioapic;
  65 } ICH9LPCState;
  66
  67 Object *ich9_lpc_find(void);
  68
  69 #define Q35_MASK(bit, ms_bit, ls_bit) \
  70 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
  71
  72 /* ICH9: Chipset Configuration Registers */
  73 #define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)
  74
  75 #define ICH9_CC
  76 #define ICH9_CC_D28IP                           0x310C
  77 #define ICH9_CC_D28IP_SHIFT                     4
  78 #define ICH9_CC_D28IP_MASK                      0xf
  79 #define ICH9_CC_D28IP_DEFAULT                   0x00214321
  80 #define ICH9_CC_D31IR                           0x3140
  81 #define ICH9_CC_D30IR                           0x3142
  82 #define ICH9_CC_D29IR                           0x3144
  83 #define ICH9_CC_D28IR                           0x3146
  84 #define ICH9_CC_D27IR                           0x3148
  85 #define ICH9_CC_D26IR                           0x314C
  86 #define ICH9_CC_D25IR                           0x3150
  87 #define ICH9_CC_DIR_DEFAULT                     0x3210
  88 #define ICH9_CC_D30IR_DEFAULT                   0x0
  89 #define ICH9_CC_DIR_SHIFT                       4
  90 #define ICH9_CC_DIR_MASK                        0x7
  91 #define ICH9_CC_OIC                             0x31FF
  92 #define ICH9_CC_OIC_AEN                         0x1
  93
  94 /* D28:F[0-5] */
  95 #define ICH9_PCIE_DEV                           28
  96 #define ICH9_PCIE_FUNC_MAX                      6
  97
  98
  99 /* D29:F0 USB UHCI Controller #1 */
 100 #define ICH9_USB_UHCI1_DEV                      29
 101 #define ICH9_USB_UHCI1_FUNC                     0
 102
 103 /* D30:F0 DMI-to-PCI bridge */
 104 #define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
 105 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0
 106
 107 #define ICH9_D2P_BRIDGE_DEV                     30
 108 #define ICH9_D2P_BRIDGE_FUNC                    0
 109
 110 #define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)
 111
 112 #define ICH9_D2P_A2_REVISION                    0x92
 113
 114 /* D31:F0 LPC Processor Interface */
 115 #define ICH9_RST_CNT_IOPORT                     0xCF9
 116
 117 /* D31:F1 LPC controller */
 118 #define ICH9_A2_LPC                             "ICH9 A2 LPC"
 119 #define ICH9_A2_LPC_SAVEVM_VERSION              0
 120
 121 #define ICH9_LPC_DEV                            31
 122 #define ICH9_LPC_FUNC                           0
 123
 124 #define ICH9_A2_LPC_REVISION                    0x2
 125 #define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */
 126
 127 #define ICH9_LPC_PMBASE                         0x40
 128 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK       Q35_MASK(32, 15, 7)
 129 #define ICH9_LPC_PMBASE_RTE                     0x1
 130 #define ICH9_LPC_PMBASE_DEFAULT                 0x1
 131 #define ICH9_LPC_ACPI_CTRL                      0x44
 132 #define ICH9_LPC_ACPI_CTRL_ACPI_EN              0x80
 133 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK     Q35_MASK(8, 2, 0)
 134 #define ICH9_LPC_ACPI_CTRL_9                    0x0
 135 #define ICH9_LPC_ACPI_CTRL_10                   0x1
 136 #define ICH9_LPC_ACPI_CTRL_11                   0x2
 137 #define ICH9_LPC_ACPI_CTRL_20                   0x4
 138 #define ICH9_LPC_ACPI_CTRL_21                   0x5
 139 #define ICH9_LPC_ACPI_CTRL_DEFAULT              0x0
 140
 141 #define ICH9_LPC_PIRQA_ROUT                     0x60
 142 #define ICH9_LPC_PIRQB_ROUT                     0x61
 143 #define ICH9_LPC_PIRQC_ROUT                     0x62
 144 #define ICH9_LPC_PIRQD_ROUT                     0x63
 145
 146 #define ICH9_LPC_PIRQE_ROUT                     0x68
 147 #define ICH9_LPC_PIRQF_ROUT                     0x69
 148 #define ICH9_LPC_PIRQG_ROUT                     0x6a
 149 #define ICH9_LPC_PIRQH_ROUT                     0x6b
 150
 151 #define ICH9_LPC_PIRQ_ROUT_IRQEN                0x80
 152 #define ICH9_LPC_PIRQ_ROUT_MASK                 Q35_MASK(8, 3, 0)
 153 #define ICH9_LPC_PIRQ_ROUT_DEFAULT              0x80
 154
 155 #define ICH9_LPC_GEN_PMCON_1                    0xa0
 156 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK           (1 << 4)
 157 #define ICH9_LPC_GEN_PMCON_2                    0xa2
 158 #define ICH9_LPC_GEN_PMCON_3                    0xa4
 159 #define ICH9_LPC_GEN_PMCON_LOCK                 0xa6
 160
 161 #define ICH9_LPC_RCBA                           0xf0
 162 #define ICH9_LPC_RCBA_BA_MASK                   Q35_MASK(32, 31, 14)
 163 #define ICH9_LPC_RCBA_EN                        0x1
 164 #define ICH9_LPC_RCBA_DEFAULT                   0x0
 165
 166 #define ICH9_LPC_PIC_NUM_PINS                   16
 167 #define ICH9_LPC_IOAPIC_NUM_PINS                24
 168
 169 /* D31:F2 SATA Controller #1 */
 170 #define ICH9_SATA1_DEV                          31
 171 #define ICH9_SATA1_FUNC                         2
 172
 173 /* D30:F1 power management I/O registers
 174    offset from the address ICH9_LPC_PMBASE */
 175
 176 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
 177 #define ICH9_PMIO_SIZE                          128
 178 #define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)
 179
 180 #define ICH9_PMIO_PM1_STS                       0x00
 181 #define ICH9_PMIO_PM1_EN                        0x02
 182 #define ICH9_PMIO_PM1_CNT                       0x04
 183 #define ICH9_PMIO_PM1_TMR                       0x08
 184 #define ICH9_PMIO_GPE0_STS                      0x20
 185 #define ICH9_PMIO_GPE0_EN                       0x28
 186 #define ICH9_PMIO_GPE0_LEN                      16
 187 #define ICH9_PMIO_SMI_EN                        0x30
 188 #define ICH9_PMIO_SMI_EN_APMC_EN                (1 << 5)
 189 #define ICH9_PMIO_SMI_STS                       0x34
 190
 191 /* FADT ACPI_ENABLE/ACPI_DISABLE */
 192 #define ICH9_APM_ACPI_ENABLE                    0x2
 193 #define ICH9_APM_ACPI_DISABLE                   0x3
 194
 195
 196 /* D31:F3 SMBus controller */
 197 #define ICH9_A2_SMB_REVISION                    0x02
 198 #define ICH9_SMB_PI                             0x00
 199
 200 #define ICH9_SMB_SMBMBAR0                       0x10
 201 #define ICH9_SMB_SMBMBAR1                       0x14
 202 #define ICH9_SMB_SMBM_BAR                       0
 203 #define ICH9_SMB_SMBM_SIZE                      (1 << 8)
 204 #define ICH9_SMB_SMB_BASE                       0x20
 205 #define ICH9_SMB_SMB_BASE_BAR                   4
 206 #define ICH9_SMB_SMB_BASE_SIZE                  (1 << 5)
 207 #define ICH9_SMB_HOSTC                          0x40
 208 #define ICH9_SMB_HOSTC_SSRESET                  ((uint8_t)(1 << 3))
 209 #define ICH9_SMB_HOSTC_I2C_EN                   ((uint8_t)(1 << 2))
 210 #define ICH9_SMB_HOSTC_SMB_SMI_EN               ((uint8_t)(1 << 1))
 211 #define ICH9_SMB_HOSTC_HST_EN                   ((uint8_t)(1 << 0))
 212
 213 /* D31:F3 SMBus I/O and memory mapped I/O registers */
 214 #define ICH9_SMB_DEV                            31
 215 #define ICH9_SMB_FUNC                           3
 216
 217 #define ICH9_SMB_HST_STS                        0x00
 218 #define ICH9_SMB_HST_CNT                        0x02
 219 #define ICH9_SMB_HST_CMD                        0x03
 220 #define ICH9_SMB_XMIT_SLVA                      0x04
 221 #define ICH9_SMB_HST_D0                         0x05
 222 #define ICH9_SMB_HST_D1                         0x06
 223 #define ICH9_SMB_HOST_BLOCK_DB                  0x07
 224
 225 #endif /* HW_ICH9_H */