2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "sysemu/dma.h"
26 #include "hw/i386/x86-iommu.h"
28 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
29 #define INTEL_IOMMU_DEVICE(obj) \
30 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
32 /* DMAR Hardware Unit Definition address (IOMMU unit) */
33 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
35 #define VTD_PCI_BUS_MAX 256
36 #define VTD_PCI_SLOT_MAX 32
37 #define VTD_PCI_FUNC_MAX 8
38 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
39 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
40 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
41 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
43 #define DMAR_REG_SIZE 0x230
44 #define VTD_HOST_ADDRESS_WIDTH 39
45 #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)
47 #define DMAR_REPORT_F_INTR (1)
49 typedef struct VTDContextEntry VTDContextEntry
;
50 typedef struct VTDContextCacheEntry VTDContextCacheEntry
;
51 typedef struct IntelIOMMUState IntelIOMMUState
;
52 typedef struct VTDAddressSpace VTDAddressSpace
;
53 typedef struct VTDIOTLBEntry VTDIOTLBEntry
;
54 typedef struct VTDBus VTDBus
;
57 struct VTDContextEntry
{
62 struct VTDContextCacheEntry
{
63 /* The cache entry is obsolete if
64 * context_cache_gen!=IntelIOMMUState.context_cache_gen
66 uint32_t context_cache_gen
;
67 struct VTDContextEntry context_entry
;
70 struct VTDAddressSpace
{
75 IntelIOMMUState
*iommu_state
;
76 VTDContextCacheEntry context_cache_entry
;
80 PCIBus
* bus
; /* A reference to the bus to provide translation for */
81 VTDAddressSpace
*dev_as
[0]; /* A table of VTDAddressSpace objects indexed by devfn */
84 struct VTDIOTLBEntry
{
93 /* The iommu (DMAR) device state struct */
94 struct IntelIOMMUState
{
95 X86IOMMUState x86_iommu
;
97 uint8_t csr
[DMAR_REG_SIZE
]; /* register values */
98 uint8_t wmask
[DMAR_REG_SIZE
]; /* R/W bytes */
99 uint8_t w1cmask
[DMAR_REG_SIZE
]; /* RW1C(Write 1 to Clear) bytes */
100 uint8_t womask
[DMAR_REG_SIZE
]; /* WO (write only - read returns 0) */
103 dma_addr_t root
; /* Current root table pointer */
104 bool root_extended
; /* Type of root table (extended or not) */
105 bool dmar_enabled
; /* Set if DMA remapping is enabled */
107 uint16_t iq_head
; /* Current invalidation queue head */
108 uint16_t iq_tail
; /* Current invalidation queue tail */
109 dma_addr_t iq
; /* Current invalidation queue pointer */
110 uint16_t iq_size
; /* IQ Size in number of entries */
111 bool qi_enabled
; /* Set if the QI is enabled */
112 uint8_t iq_last_desc_type
; /* The type of last completed descriptor */
114 /* The index of the Fault Recording Register to be used next.
115 * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
117 uint16_t next_frcd_reg
;
119 uint64_t cap
; /* The value of capability reg */
120 uint64_t ecap
; /* The value of extended capability reg */
122 uint32_t context_cache_gen
; /* Should be in [1,MAX] */
123 GHashTable
*iotlb
; /* IOTLB */
125 MemoryRegionIOMMUOps iommu_ops
;
126 GHashTable
*vtd_as_by_busptr
; /* VTDBus objects indexed by PCIBus* reference */
127 VTDBus
*vtd_as_by_bus_num
[VTD_PCI_BUS_MAX
]; /* VTDBus objects indexed by bus number */
129 /* interrupt remapping */
130 bool intr_enabled
; /* Whether guest enabled IR */
131 dma_addr_t intr_root
; /* Interrupt remapping table pointer */
132 uint32_t intr_size
; /* Number of IR table entries */
135 /* Find the VTD Address space associated with the given bus pointer,
136 * create a new one if none exists
138 VTDAddressSpace
*vtd_find_add_as(IntelIOMMUState
*s
, PCIBus
*bus
, int devfn
);