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1 #ifndef HW_PC_H
2 #define HW_PC_H
3
4 #include "qemu-common.h"
5 #include "exec/memory.h"
6 #include "hw/boards.h"
7 #include "hw/isa/isa.h"
8 #include "hw/block/fdc.h"
9 #include "net/net.h"
10 #include "hw/i386/ioapic.h"
11
12 #include "qemu/range.h"
13 #include "qemu/bitmap.h"
14 #include "sysemu/sysemu.h"
15 #include "hw/pci/pci.h"
16 #include "hw/boards.h"
17 #include "hw/compat.h"
18
19 #define HPET_INTCAP "hpet-intcap"
20
21 /**
22 * PCMachineState:
23 * @hotplug_memory_base: address in guest RAM address space where hotplug memory
24 * address space begins.
25 * @hotplug_memory: hotplug memory addess space container
26 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
27 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
28 * backend's alignment value if provided
29 */
30 struct PCMachineState {
31 /*< private >*/
32 MachineState parent_obj;
33
34 /* <public> */
35 ram_addr_t hotplug_memory_base;
36 MemoryRegion hotplug_memory;
37
38 HotplugHandler *acpi_dev;
39 ISADevice *rtc;
40
41 uint64_t max_ram_below_4g;
42 OnOffAuto vmport;
43 bool enforce_aligned_dimm;
44 };
45
46 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
47 #define PC_MACHINE_MEMHP_REGION_SIZE "hotplug-memory-region-size"
48 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
49 #define PC_MACHINE_VMPORT "vmport"
50 #define PC_MACHINE_ENFORCE_ALIGNED_DIMM "enforce-aligned-dimm"
51
52 /**
53 * PCMachineClass:
54 * @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler
55 */
56 struct PCMachineClass {
57 /*< private >*/
58 MachineClass parent_class;
59
60 /*< public >*/
61 HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
62 DeviceState *dev);
63 };
64
65 typedef struct PCMachineState PCMachineState;
66 typedef struct PCMachineClass PCMachineClass;
67
68 #define TYPE_PC_MACHINE "generic-pc-machine"
69 #define PC_MACHINE(obj) \
70 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
71 #define PC_MACHINE_GET_CLASS(obj) \
72 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
73 #define PC_MACHINE_CLASS(klass) \
74 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
75
76 void qemu_register_pc_machine(QEMUMachine *m);
77
78 /* PC-style peripherals (also used by other machines). */
79
80 typedef struct PcPciInfo {
81 Range w32;
82 Range w64;
83 } PcPciInfo;
84
85 #define ACPI_PM_PROP_S3_DISABLED "disable_s3"
86 #define ACPI_PM_PROP_S4_DISABLED "disable_s4"
87 #define ACPI_PM_PROP_S4_VAL "s4_val"
88 #define ACPI_PM_PROP_SCI_INT "sci_int"
89 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
90 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
91 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
92 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
93 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
94
95 struct PcGuestInfo {
96 bool isapc_ram_fw;
97 hwaddr ram_size, ram_size_below_4g;
98 unsigned apic_id_limit;
99 bool apic_xrupt_override;
100 uint64_t numa_nodes;
101 uint64_t *node_mem;
102 uint64_t *node_cpu;
103 FWCfgState *fw_cfg;
104 int legacy_acpi_table_size;
105 bool has_acpi_build;
106 bool has_reserved_memory;
107 bool rsdp_in_ram;
108 };
109
110 /* parallel.c */
111 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
112 {
113 DeviceState *dev;
114 ISADevice *isadev;
115
116 isadev = isa_try_create(bus, "isa-parallel");
117 if (!isadev) {
118 return false;
119 }
120 dev = DEVICE(isadev);
121 qdev_prop_set_uint32(dev, "index", index);
122 qdev_prop_set_chr(dev, "chardev", chr);
123 if (qdev_init(dev) < 0) {
124 return false;
125 }
126 return true;
127 }
128
129 bool parallel_mm_init(MemoryRegion *address_space,
130 hwaddr base, int it_shift, qemu_irq irq,
131 CharDriverState *chr);
132
133 /* i8259.c */
134
135 extern DeviceState *isa_pic;
136 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
137 qemu_irq *kvm_i8259_init(ISABus *bus);
138 int pic_read_irq(DeviceState *d);
139 int pic_get_output(DeviceState *d);
140 void hmp_info_pic(Monitor *mon, const QDict *qdict);
141 void hmp_info_irq(Monitor *mon, const QDict *qdict);
142
143 /* Global System Interrupts */
144
145 #define GSI_NUM_PINS IOAPIC_NUM_PINS
146
147 typedef struct GSIState {
148 qemu_irq i8259_irq[ISA_NUM_IRQS];
149 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
150 } GSIState;
151
152 void gsi_handler(void *opaque, int n, int level);
153
154 /* vmport.c */
155 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
156
157 static inline void vmport_init(ISABus *bus)
158 {
159 isa_create_simple(bus, "vmport");
160 }
161
162 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
163 void vmmouse_get_data(uint32_t *data);
164 void vmmouse_set_data(const uint32_t *data);
165
166 /* pckbd.c */
167
168 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
169 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
170 MemoryRegion *region, ram_addr_t size,
171 hwaddr mask);
172 void i8042_isa_mouse_fake_event(void *opaque);
173 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
174
175 /* pc.c */
176 extern int fd_bootchk;
177
178 void pc_register_ferr_irq(qemu_irq irq);
179 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
180
181 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
182 void pc_hot_add_cpu(const int64_t id, Error **errp);
183 void pc_acpi_init(const char *default_dsdt);
184
185 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
186 ram_addr_t above_4g_mem_size);
187
188 void pc_set_legacy_acpi_data_size(void);
189
190 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
191 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
192 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
193 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
194 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
195 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
196
197
198 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
199 MemoryRegion *pci_address_space);
200
201 FWCfgState *xen_load_linux(const char *kernel_filename,
202 const char *kernel_cmdline,
203 const char *initrd_filename,
204 ram_addr_t below_4g_mem_size,
205 PcGuestInfo *guest_info);
206 FWCfgState *pc_memory_init(MachineState *machine,
207 MemoryRegion *system_memory,
208 ram_addr_t below_4g_mem_size,
209 ram_addr_t above_4g_mem_size,
210 MemoryRegion *rom_memory,
211 MemoryRegion **ram_memory,
212 PcGuestInfo *guest_info);
213 qemu_irq *pc_allocate_cpu_irq(void);
214 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
215 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
216 ISADevice **rtc_state,
217 ISADevice **floppy,
218 bool no_vmport,
219 uint32 hpet_irqs);
220 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
221 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
222 const char *boot_device, MachineState *machine,
223 ISADevice *floppy, BusState *ide0, BusState *ide1,
224 ISADevice *s);
225 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
226 void pc_pci_device_init(PCIBus *pci_bus);
227
228 typedef void (*cpu_set_smm_t)(int smm, void *arg);
229 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
230
231 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
232
233 /* acpi_piix.c */
234
235 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
236 qemu_irq sci_irq, qemu_irq smi_irq,
237 int kvm_enabled, FWCfgState *fw_cfg,
238 DeviceState **piix4_pm);
239 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
240
241 /* hpet.c */
242 extern int no_hpet;
243
244 /* piix_pci.c */
245 struct PCII440FXState;
246 typedef struct PCII440FXState PCII440FXState;
247
248 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
249 ISABus **isa_bus, qemu_irq *pic,
250 MemoryRegion *address_space_mem,
251 MemoryRegion *address_space_io,
252 ram_addr_t ram_size,
253 ram_addr_t below_4g_mem_size,
254 ram_addr_t above_4g_mem_size,
255 MemoryRegion *pci_memory,
256 MemoryRegion *ram_memory);
257
258 PCIBus *find_i440fx(void);
259 /* piix4.c */
260 extern PCIDevice *piix4_dev;
261 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
262
263 /* vga.c */
264 enum vga_retrace_method {
265 VGA_RETRACE_DUMB,
266 VGA_RETRACE_PRECISE
267 };
268
269 extern enum vga_retrace_method vga_retrace_method;
270
271 int isa_vga_mm_init(hwaddr vram_base,
272 hwaddr ctrl_base, int it_shift,
273 MemoryRegion *address_space);
274
275 /* ne2000.c */
276 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
277 {
278 DeviceState *dev;
279 ISADevice *isadev;
280
281 qemu_check_nic_model(nd, "ne2k_isa");
282
283 isadev = isa_try_create(bus, "ne2k_isa");
284 if (!isadev) {
285 return false;
286 }
287 dev = DEVICE(isadev);
288 qdev_prop_set_uint32(dev, "iobase", base);
289 qdev_prop_set_uint32(dev, "irq", irq);
290 qdev_set_nic_properties(dev, nd);
291 qdev_init_nofail(dev);
292 return true;
293 }
294
295 /* pc_sysfw.c */
296 void pc_system_firmware_init(MemoryRegion *rom_memory,
297 bool isapc_ram_fw);
298
299 /* pvpanic.c */
300 uint16_t pvpanic_port(void);
301
302 /* e820 types */
303 #define E820_RAM 1
304 #define E820_RESERVED 2
305 #define E820_ACPI 3
306 #define E820_NVS 4
307 #define E820_UNUSABLE 5
308
309 int e820_add_entry(uint64_t, uint64_t, uint32_t);
310 int e820_get_num_entries(void);
311 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
312
313 #define PC_COMPAT_2_0 \
314 HW_COMPAT_2_1, \
315 {\
316 .driver = "virtio-scsi-pci",\
317 .property = "any_layout",\
318 .value = "off",\
319 },{\
320 .driver = "PIIX4_PM",\
321 .property = "memory-hotplug-support",\
322 .value = "off",\
323 },\
324 {\
325 .driver = "apic",\
326 .property = "version",\
327 .value = stringify(0x11),\
328 },\
329 {\
330 .driver = "nec-usb-xhci",\
331 .property = "superspeed-ports-first",\
332 .value = "off",\
333 },\
334 {\
335 .driver = "nec-usb-xhci",\
336 .property = "force-pcie-endcap",\
337 .value = "on",\
338 },\
339 {\
340 .driver = "pci-serial",\
341 .property = "prog_if",\
342 .value = stringify(0),\
343 },\
344 {\
345 .driver = "pci-serial-2x",\
346 .property = "prog_if",\
347 .value = stringify(0),\
348 },\
349 {\
350 .driver = "pci-serial-4x",\
351 .property = "prog_if",\
352 .value = stringify(0),\
353 },\
354 {\
355 .driver = "virtio-net-pci",\
356 .property = "guest_announce",\
357 .value = "off",\
358 },\
359 {\
360 .driver = "ICH9-LPC",\
361 .property = "memory-hotplug-support",\
362 .value = "off",\
363 },{\
364 .driver = "xio3130-downstream",\
365 .property = COMPAT_PROP_PCP,\
366 .value = "off",\
367 },{\
368 .driver = "ioh3420",\
369 .property = COMPAT_PROP_PCP,\
370 .value = "off",\
371 }
372
373 #define PC_COMPAT_1_7 \
374 PC_COMPAT_2_0, \
375 {\
376 .driver = TYPE_USB_DEVICE,\
377 .property = "msos-desc",\
378 .value = "no",\
379 },\
380 {\
381 .driver = "PIIX4_PM",\
382 .property = "acpi-pci-hotplug-with-bridge-support",\
383 .value = "off",\
384 },\
385 {\
386 .driver = "hpet",\
387 .property = HPET_INTCAP,\
388 .value = stringify(4),\
389 }
390
391 #define PC_COMPAT_1_6 \
392 PC_COMPAT_1_7, \
393 {\
394 .driver = "e1000",\
395 .property = "mitigation",\
396 .value = "off",\
397 },{\
398 .driver = "qemu64-" TYPE_X86_CPU,\
399 .property = "model",\
400 .value = stringify(2),\
401 },{\
402 .driver = "qemu32-" TYPE_X86_CPU,\
403 .property = "model",\
404 .value = stringify(3),\
405 },{\
406 .driver = "i440FX-pcihost",\
407 .property = "short_root_bus",\
408 .value = stringify(1),\
409 },{\
410 .driver = "q35-pcihost",\
411 .property = "short_root_bus",\
412 .value = stringify(1),\
413 }
414
415 #define PC_COMPAT_1_5 \
416 PC_COMPAT_1_6, \
417 {\
418 .driver = "Conroe-" TYPE_X86_CPU,\
419 .property = "model",\
420 .value = stringify(2),\
421 },{\
422 .driver = "Conroe-" TYPE_X86_CPU,\
423 .property = "level",\
424 .value = stringify(2),\
425 },{\
426 .driver = "Penryn-" TYPE_X86_CPU,\
427 .property = "model",\
428 .value = stringify(2),\
429 },{\
430 .driver = "Penryn-" TYPE_X86_CPU,\
431 .property = "level",\
432 .value = stringify(2),\
433 },{\
434 .driver = "Nehalem-" TYPE_X86_CPU,\
435 .property = "model",\
436 .value = stringify(2),\
437 },{\
438 .driver = "Nehalem-" TYPE_X86_CPU,\
439 .property = "level",\
440 .value = stringify(2),\
441 },{\
442 .driver = "virtio-net-pci",\
443 .property = "any_layout",\
444 .value = "off",\
445 },{\
446 .driver = TYPE_X86_CPU,\
447 .property = "pmu",\
448 .value = "on",\
449 },{\
450 .driver = "i440FX-pcihost",\
451 .property = "short_root_bus",\
452 .value = stringify(0),\
453 },{\
454 .driver = "q35-pcihost",\
455 .property = "short_root_bus",\
456 .value = stringify(0),\
457 }
458
459 #define PC_COMPAT_1_4 \
460 PC_COMPAT_1_5, \
461 {\
462 .driver = "scsi-hd",\
463 .property = "discard_granularity",\
464 .value = stringify(0),\
465 },{\
466 .driver = "scsi-cd",\
467 .property = "discard_granularity",\
468 .value = stringify(0),\
469 },{\
470 .driver = "scsi-disk",\
471 .property = "discard_granularity",\
472 .value = stringify(0),\
473 },{\
474 .driver = "ide-hd",\
475 .property = "discard_granularity",\
476 .value = stringify(0),\
477 },{\
478 .driver = "ide-cd",\
479 .property = "discard_granularity",\
480 .value = stringify(0),\
481 },{\
482 .driver = "ide-drive",\
483 .property = "discard_granularity",\
484 .value = stringify(0),\
485 },{\
486 .driver = "virtio-blk-pci",\
487 .property = "discard_granularity",\
488 .value = stringify(0),\
489 },{\
490 .driver = "virtio-serial-pci",\
491 .property = "vectors",\
492 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
493 .value = stringify(0xFFFFFFFF),\
494 },{ \
495 .driver = "virtio-net-pci", \
496 .property = "ctrl_guest_offloads", \
497 .value = "off", \
498 },{\
499 .driver = "e1000",\
500 .property = "romfile",\
501 .value = "pxe-e1000.rom",\
502 },{\
503 .driver = "ne2k_pci",\
504 .property = "romfile",\
505 .value = "pxe-ne2k_pci.rom",\
506 },{\
507 .driver = "pcnet",\
508 .property = "romfile",\
509 .value = "pxe-pcnet.rom",\
510 },{\
511 .driver = "rtl8139",\
512 .property = "romfile",\
513 .value = "pxe-rtl8139.rom",\
514 },{\
515 .driver = "virtio-net-pci",\
516 .property = "romfile",\
517 .value = "pxe-virtio.rom",\
518 },{\
519 .driver = "486-" TYPE_X86_CPU,\
520 .property = "model",\
521 .value = stringify(0),\
522 }
523
524 #define PC_COMMON_MACHINE_OPTIONS \
525 .default_boot_order = "cad"
526
527 #define PC_DEFAULT_MACHINE_OPTIONS \
528 PC_COMMON_MACHINE_OPTIONS, \
529 .hot_add_cpu = pc_hot_add_cpu, \
530 .max_cpus = 255
531
532 #endif