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xhci PCIe endpoint migration compatibility fix
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1 #ifndef HW_PC_H
2 #define HW_PC_H
3
4 #include "qemu-common.h"
5 #include "exec/memory.h"
6 #include "hw/boards.h"
7 #include "hw/isa/isa.h"
8 #include "hw/block/fdc.h"
9 #include "net/net.h"
10 #include "hw/i386/ioapic.h"
11
12 #include "qemu/range.h"
13 #include "qemu/bitmap.h"
14 #include "sysemu/sysemu.h"
15 #include "hw/pci/pci.h"
16 #include "hw/boards.h"
17
18 #define HPET_INTCAP "hpet-intcap"
19
20 /**
21 * PCMachineState:
22 * @hotplug_memory_base: address in guest RAM address space where hotplug memory
23 * address space begins.
24 * @hotplug_memory: hotplug memory addess space container
25 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
26 */
27 struct PCMachineState {
28 /*< private >*/
29 MachineState parent_obj;
30
31 /* <public> */
32 ram_addr_t hotplug_memory_base;
33 MemoryRegion hotplug_memory;
34
35 HotplugHandler *acpi_dev;
36
37 uint64_t max_ram_below_4g;
38 };
39
40 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
41 #define PC_MACHINE_MEMHP_REGION_SIZE "hotplug-memory-region-size"
42 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
43
44 /**
45 * PCMachineClass:
46 * @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler
47 */
48 struct PCMachineClass {
49 /*< private >*/
50 MachineClass parent_class;
51
52 /*< public >*/
53 HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
54 DeviceState *dev);
55 };
56
57 typedef struct PCMachineState PCMachineState;
58 typedef struct PCMachineClass PCMachineClass;
59
60 #define TYPE_PC_MACHINE "generic-pc-machine"
61 #define PC_MACHINE(obj) \
62 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
63 #define PC_MACHINE_GET_CLASS(obj) \
64 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
65 #define PC_MACHINE_CLASS(klass) \
66 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
67
68 void qemu_register_pc_machine(QEMUMachine *m);
69
70 /* PC-style peripherals (also used by other machines). */
71
72 typedef struct PcPciInfo {
73 Range w32;
74 Range w64;
75 } PcPciInfo;
76
77 #define ACPI_PM_PROP_S3_DISABLED "disable_s3"
78 #define ACPI_PM_PROP_S4_DISABLED "disable_s4"
79 #define ACPI_PM_PROP_S4_VAL "s4_val"
80 #define ACPI_PM_PROP_SCI_INT "sci_int"
81 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
82 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
83 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
84 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
85 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
86
87 struct PcGuestInfo {
88 bool isapc_ram_fw;
89 hwaddr ram_size, ram_size_below_4g;
90 unsigned apic_id_limit;
91 bool apic_xrupt_override;
92 uint64_t numa_nodes;
93 uint64_t *node_mem;
94 uint64_t *node_cpu;
95 FWCfgState *fw_cfg;
96 int legacy_acpi_table_size;
97 bool has_acpi_build;
98 bool has_reserved_memory;
99 };
100
101 /* parallel.c */
102 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
103 {
104 DeviceState *dev;
105 ISADevice *isadev;
106
107 isadev = isa_try_create(bus, "isa-parallel");
108 if (!isadev) {
109 return false;
110 }
111 dev = DEVICE(isadev);
112 qdev_prop_set_uint32(dev, "index", index);
113 qdev_prop_set_chr(dev, "chardev", chr);
114 if (qdev_init(dev) < 0) {
115 return false;
116 }
117 return true;
118 }
119
120 bool parallel_mm_init(MemoryRegion *address_space,
121 hwaddr base, int it_shift, qemu_irq irq,
122 CharDriverState *chr);
123
124 /* i8259.c */
125
126 extern DeviceState *isa_pic;
127 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
128 qemu_irq *kvm_i8259_init(ISABus *bus);
129 int pic_read_irq(DeviceState *d);
130 int pic_get_output(DeviceState *d);
131 void pic_info(Monitor *mon, const QDict *qdict);
132 void irq_info(Monitor *mon, const QDict *qdict);
133
134 /* Global System Interrupts */
135
136 #define GSI_NUM_PINS IOAPIC_NUM_PINS
137
138 typedef struct GSIState {
139 qemu_irq i8259_irq[ISA_NUM_IRQS];
140 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
141 } GSIState;
142
143 void gsi_handler(void *opaque, int n, int level);
144
145 /* vmport.c */
146 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
147
148 static inline void vmport_init(ISABus *bus)
149 {
150 isa_create_simple(bus, "vmport");
151 }
152
153 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
154 void vmmouse_get_data(uint32_t *data);
155 void vmmouse_set_data(const uint32_t *data);
156
157 /* pckbd.c */
158
159 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
160 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
161 MemoryRegion *region, ram_addr_t size,
162 hwaddr mask);
163 void i8042_isa_mouse_fake_event(void *opaque);
164 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
165
166 /* pc.c */
167 extern int fd_bootchk;
168
169 void pc_register_ferr_irq(qemu_irq irq);
170 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
171
172 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
173 void pc_hot_add_cpu(const int64_t id, Error **errp);
174 void pc_acpi_init(const char *default_dsdt);
175
176 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
177 ram_addr_t above_4g_mem_size);
178
179 void pc_set_legacy_acpi_data_size(void);
180
181 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
182 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
183 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
184 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
185 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
186 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
187
188
189 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
190 MemoryRegion *pci_address_space);
191
192 FWCfgState *xen_load_linux(const char *kernel_filename,
193 const char *kernel_cmdline,
194 const char *initrd_filename,
195 ram_addr_t below_4g_mem_size,
196 PcGuestInfo *guest_info);
197 FWCfgState *pc_memory_init(MachineState *machine,
198 MemoryRegion *system_memory,
199 ram_addr_t below_4g_mem_size,
200 ram_addr_t above_4g_mem_size,
201 MemoryRegion *rom_memory,
202 MemoryRegion **ram_memory,
203 PcGuestInfo *guest_info);
204 qemu_irq *pc_allocate_cpu_irq(void);
205 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
206 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
207 ISADevice **rtc_state,
208 ISADevice **floppy,
209 bool no_vmport,
210 uint32 hpet_irqs);
211 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
212 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
213 const char *boot_device,
214 ISADevice *floppy, BusState *ide0, BusState *ide1,
215 ISADevice *s);
216 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
217 void pc_pci_device_init(PCIBus *pci_bus);
218
219 typedef void (*cpu_set_smm_t)(int smm, void *arg);
220 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
221
222 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
223
224 /* acpi_piix.c */
225
226 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
227 qemu_irq sci_irq, qemu_irq smi_irq,
228 int kvm_enabled, FWCfgState *fw_cfg,
229 DeviceState **piix4_pm);
230 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
231
232 /* hpet.c */
233 extern int no_hpet;
234
235 /* piix_pci.c */
236 struct PCII440FXState;
237 typedef struct PCII440FXState PCII440FXState;
238
239 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
240 ISABus **isa_bus, qemu_irq *pic,
241 MemoryRegion *address_space_mem,
242 MemoryRegion *address_space_io,
243 ram_addr_t ram_size,
244 ram_addr_t below_4g_mem_size,
245 ram_addr_t above_4g_mem_size,
246 MemoryRegion *pci_memory,
247 MemoryRegion *ram_memory);
248
249 PCIBus *find_i440fx(void);
250 /* piix4.c */
251 extern PCIDevice *piix4_dev;
252 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
253
254 /* vga.c */
255 enum vga_retrace_method {
256 VGA_RETRACE_DUMB,
257 VGA_RETRACE_PRECISE
258 };
259
260 extern enum vga_retrace_method vga_retrace_method;
261
262 int isa_vga_mm_init(hwaddr vram_base,
263 hwaddr ctrl_base, int it_shift,
264 MemoryRegion *address_space);
265
266 /* ne2000.c */
267 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
268 {
269 DeviceState *dev;
270 ISADevice *isadev;
271
272 qemu_check_nic_model(nd, "ne2k_isa");
273
274 isadev = isa_try_create(bus, "ne2k_isa");
275 if (!isadev) {
276 return false;
277 }
278 dev = DEVICE(isadev);
279 qdev_prop_set_uint32(dev, "iobase", base);
280 qdev_prop_set_uint32(dev, "irq", irq);
281 qdev_set_nic_properties(dev, nd);
282 qdev_init_nofail(dev);
283 return true;
284 }
285
286 /* pc_sysfw.c */
287 void pc_system_firmware_init(MemoryRegion *rom_memory,
288 bool isapc_ram_fw);
289
290 /* pvpanic.c */
291 uint16_t pvpanic_port(void);
292
293 /* e820 types */
294 #define E820_RAM 1
295 #define E820_RESERVED 2
296 #define E820_ACPI 3
297 #define E820_NVS 4
298 #define E820_UNUSABLE 5
299
300 int e820_add_entry(uint64_t, uint64_t, uint32_t);
301 int e820_get_num_entries(void);
302 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
303
304 #define PC_COMPAT_2_1 \
305 {\
306 .driver = "intel-hda",\
307 .property = "old_msi_addr",\
308 .value = "on",\
309 }
310
311 #define PC_COMPAT_2_0 \
312 PC_COMPAT_2_1, \
313 {\
314 .driver = "virtio-scsi-pci",\
315 .property = "any_layout",\
316 .value = "off",\
317 },{\
318 .driver = "PIIX4_PM",\
319 .property = "memory-hotplug-support",\
320 .value = "off",\
321 },\
322 {\
323 .driver = "apic",\
324 .property = "version",\
325 .value = stringify(0x11),\
326 },\
327 {\
328 .driver = "nec-usb-xhci",\
329 .property = "superspeed-ports-first",\
330 .value = "off",\
331 },\
332 {\
333 .driver = "nec-usb-xhci",\
334 .property = "force-pcie-endcap",\
335 .value = "on",\
336 },\
337 {\
338 .driver = "pci-serial",\
339 .property = "prog_if",\
340 .value = stringify(0),\
341 },\
342 {\
343 .driver = "pci-serial-2x",\
344 .property = "prog_if",\
345 .value = stringify(0),\
346 },\
347 {\
348 .driver = "pci-serial-4x",\
349 .property = "prog_if",\
350 .value = stringify(0),\
351 },\
352 {\
353 .driver = "virtio-net-pci",\
354 .property = "guest_announce",\
355 .value = "off",\
356 },\
357 {\
358 .driver = "ICH9-LPC",\
359 .property = "memory-hotplug-support",\
360 .value = "off",\
361 },{\
362 .driver = "xio3130-downstream",\
363 .property = COMPAT_PROP_PCP,\
364 .value = "off",\
365 },{\
366 .driver = "ioh3420",\
367 .property = COMPAT_PROP_PCP,\
368 .value = "off",\
369 }
370
371 #define PC_COMPAT_1_7 \
372 PC_COMPAT_2_0, \
373 {\
374 .driver = TYPE_USB_DEVICE,\
375 .property = "msos-desc",\
376 .value = "no",\
377 },\
378 {\
379 .driver = "PIIX4_PM",\
380 .property = "acpi-pci-hotplug-with-bridge-support",\
381 .value = "off",\
382 },\
383 {\
384 .driver = "hpet",\
385 .property = HPET_INTCAP,\
386 .value = stringify(4),\
387 }
388
389 #define PC_COMPAT_1_6 \
390 PC_COMPAT_1_7, \
391 {\
392 .driver = "e1000",\
393 .property = "mitigation",\
394 .value = "off",\
395 },{\
396 .driver = "qemu64-" TYPE_X86_CPU,\
397 .property = "model",\
398 .value = stringify(2),\
399 },{\
400 .driver = "qemu32-" TYPE_X86_CPU,\
401 .property = "model",\
402 .value = stringify(3),\
403 },{\
404 .driver = "i440FX-pcihost",\
405 .property = "short_root_bus",\
406 .value = stringify(1),\
407 },{\
408 .driver = "q35-pcihost",\
409 .property = "short_root_bus",\
410 .value = stringify(1),\
411 }
412
413 #define PC_COMPAT_1_5 \
414 PC_COMPAT_1_6, \
415 {\
416 .driver = "Conroe-" TYPE_X86_CPU,\
417 .property = "model",\
418 .value = stringify(2),\
419 },{\
420 .driver = "Conroe-" TYPE_X86_CPU,\
421 .property = "level",\
422 .value = stringify(2),\
423 },{\
424 .driver = "Penryn-" TYPE_X86_CPU,\
425 .property = "model",\
426 .value = stringify(2),\
427 },{\
428 .driver = "Penryn-" TYPE_X86_CPU,\
429 .property = "level",\
430 .value = stringify(2),\
431 },{\
432 .driver = "Nehalem-" TYPE_X86_CPU,\
433 .property = "model",\
434 .value = stringify(2),\
435 },{\
436 .driver = "Nehalem-" TYPE_X86_CPU,\
437 .property = "level",\
438 .value = stringify(2),\
439 },{\
440 .driver = "virtio-net-pci",\
441 .property = "any_layout",\
442 .value = "off",\
443 },{\
444 .driver = TYPE_X86_CPU,\
445 .property = "pmu",\
446 .value = "on",\
447 },{\
448 .driver = "i440FX-pcihost",\
449 .property = "short_root_bus",\
450 .value = stringify(0),\
451 },{\
452 .driver = "q35-pcihost",\
453 .property = "short_root_bus",\
454 .value = stringify(0),\
455 }
456
457 #define PC_COMPAT_1_4 \
458 PC_COMPAT_1_5, \
459 {\
460 .driver = "scsi-hd",\
461 .property = "discard_granularity",\
462 .value = stringify(0),\
463 },{\
464 .driver = "scsi-cd",\
465 .property = "discard_granularity",\
466 .value = stringify(0),\
467 },{\
468 .driver = "scsi-disk",\
469 .property = "discard_granularity",\
470 .value = stringify(0),\
471 },{\
472 .driver = "ide-hd",\
473 .property = "discard_granularity",\
474 .value = stringify(0),\
475 },{\
476 .driver = "ide-cd",\
477 .property = "discard_granularity",\
478 .value = stringify(0),\
479 },{\
480 .driver = "ide-drive",\
481 .property = "discard_granularity",\
482 .value = stringify(0),\
483 },{\
484 .driver = "virtio-blk-pci",\
485 .property = "discard_granularity",\
486 .value = stringify(0),\
487 },{\
488 .driver = "virtio-serial-pci",\
489 .property = "vectors",\
490 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
491 .value = stringify(0xFFFFFFFF),\
492 },{ \
493 .driver = "virtio-net-pci", \
494 .property = "ctrl_guest_offloads", \
495 .value = "off", \
496 },{\
497 .driver = "e1000",\
498 .property = "romfile",\
499 .value = "pxe-e1000.rom",\
500 },{\
501 .driver = "ne2k_pci",\
502 .property = "romfile",\
503 .value = "pxe-ne2k_pci.rom",\
504 },{\
505 .driver = "pcnet",\
506 .property = "romfile",\
507 .value = "pxe-pcnet.rom",\
508 },{\
509 .driver = "rtl8139",\
510 .property = "romfile",\
511 .value = "pxe-rtl8139.rom",\
512 },{\
513 .driver = "virtio-net-pci",\
514 .property = "romfile",\
515 .value = "pxe-virtio.rom",\
516 },{\
517 .driver = "486-" TYPE_X86_CPU,\
518 .property = "model",\
519 .value = stringify(0),\
520 }
521
522 #define PC_COMMON_MACHINE_OPTIONS \
523 .default_boot_order = "cad"
524
525 #define PC_DEFAULT_MACHINE_OPTIONS \
526 PC_COMMON_MACHINE_OPTIONS, \
527 .hot_add_cpu = pc_hot_add_cpu, \
528 .max_cpus = 255
529
530 #endif