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1 #ifndef HW_PC_H
2 #define HW_PC_H
3
4 #include "qemu-common.h"
5 #include "exec/memory.h"
6 #include "hw/boards.h"
7 #include "hw/isa/isa.h"
8 #include "hw/block/fdc.h"
9 #include "net/net.h"
10 #include "hw/i386/ioapic.h"
11
12 #include "qemu/range.h"
13 #include "qemu/bitmap.h"
14 #include "sysemu/sysemu.h"
15 #include "hw/pci/pci.h"
16 #include "hw/boards.h"
17 #include "hw/compat.h"
18 #include "hw/mem/pc-dimm.h"
19
20 #define HPET_INTCAP "hpet-intcap"
21
22 /**
23 * PCMachineState:
24 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
25 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
26 * backend's alignment value if provided
27 */
28 struct PCMachineState {
29 /*< private >*/
30 MachineState parent_obj;
31
32 /* <public> */
33 MemoryHotplugState hotplug_memory;
34
35 HotplugHandler *acpi_dev;
36 ISADevice *rtc;
37
38 uint64_t max_ram_below_4g;
39 OnOffAuto vmport;
40 OnOffAuto smm;
41 bool enforce_aligned_dimm;
42 };
43
44 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
45 #define PC_MACHINE_MEMHP_REGION_SIZE "hotplug-memory-region-size"
46 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
47 #define PC_MACHINE_VMPORT "vmport"
48 #define PC_MACHINE_SMM "smm"
49 #define PC_MACHINE_ENFORCE_ALIGNED_DIMM "enforce-aligned-dimm"
50
51 /**
52 * PCMachineClass:
53 * @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler
54 */
55 struct PCMachineClass {
56 /*< private >*/
57 MachineClass parent_class;
58
59 /*< public >*/
60 HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
61 DeviceState *dev);
62 };
63
64 typedef struct PCMachineState PCMachineState;
65 typedef struct PCMachineClass PCMachineClass;
66
67 #define TYPE_PC_MACHINE "generic-pc-machine"
68 #define PC_MACHINE(obj) \
69 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
70 #define PC_MACHINE_GET_CLASS(obj) \
71 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
72 #define PC_MACHINE_CLASS(klass) \
73 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
74
75 /* PC-style peripherals (also used by other machines). */
76
77 typedef struct PcPciInfo {
78 Range w32;
79 Range w64;
80 } PcPciInfo;
81
82 #define ACPI_PM_PROP_S3_DISABLED "disable_s3"
83 #define ACPI_PM_PROP_S4_DISABLED "disable_s4"
84 #define ACPI_PM_PROP_S4_VAL "s4_val"
85 #define ACPI_PM_PROP_SCI_INT "sci_int"
86 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
87 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
88 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
89 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
90 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
91 #define ACPI_PM_PROP_TCO_ENABLED "enable_tco"
92
93 struct PcGuestInfo {
94 bool isapc_ram_fw;
95 hwaddr ram_size, ram_size_below_4g;
96 unsigned apic_id_limit;
97 bool apic_xrupt_override;
98 uint64_t numa_nodes;
99 uint64_t *node_mem;
100 uint64_t *node_cpu;
101 FWCfgState *fw_cfg;
102 int legacy_acpi_table_size;
103 bool has_acpi_build;
104 bool has_reserved_memory;
105 bool rsdp_in_ram;
106 };
107
108 /* parallel.c */
109
110 void parallel_hds_isa_init(ISABus *bus, int n);
111
112 bool parallel_mm_init(MemoryRegion *address_space,
113 hwaddr base, int it_shift, qemu_irq irq,
114 CharDriverState *chr);
115
116 /* i8259.c */
117
118 extern DeviceState *isa_pic;
119 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
120 qemu_irq *kvm_i8259_init(ISABus *bus);
121 int pic_read_irq(DeviceState *d);
122 int pic_get_output(DeviceState *d);
123 void hmp_info_pic(Monitor *mon, const QDict *qdict);
124 void hmp_info_irq(Monitor *mon, const QDict *qdict);
125
126 /* Global System Interrupts */
127
128 #define GSI_NUM_PINS IOAPIC_NUM_PINS
129
130 typedef struct GSIState {
131 qemu_irq i8259_irq[ISA_NUM_IRQS];
132 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
133 } GSIState;
134
135 void gsi_handler(void *opaque, int n, int level);
136
137 /* vmport.c */
138 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
139
140 static inline void vmport_init(ISABus *bus)
141 {
142 isa_create_simple(bus, "vmport");
143 }
144
145 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
146 void vmmouse_get_data(uint32_t *data);
147 void vmmouse_set_data(const uint32_t *data);
148
149 /* pckbd.c */
150
151 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
152 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
153 MemoryRegion *region, ram_addr_t size,
154 hwaddr mask);
155 void i8042_isa_mouse_fake_event(void *opaque);
156 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
157
158 /* pc.c */
159 extern int fd_bootchk;
160
161 bool pc_machine_is_smm_enabled(PCMachineState *pcms);
162 void pc_register_ferr_irq(qemu_irq irq);
163 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
164
165 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
166 void pc_hot_add_cpu(const int64_t id, Error **errp);
167 void pc_acpi_init(const char *default_dsdt);
168
169 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
170 ram_addr_t above_4g_mem_size);
171
172 void pc_set_legacy_acpi_data_size(void);
173
174 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
175 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
176 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
177 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
178 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
179 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
180
181
182 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
183 MemoryRegion *pci_address_space);
184
185 FWCfgState *xen_load_linux(const char *kernel_filename,
186 const char *kernel_cmdline,
187 const char *initrd_filename,
188 ram_addr_t below_4g_mem_size,
189 PcGuestInfo *guest_info);
190 FWCfgState *pc_memory_init(MachineState *machine,
191 MemoryRegion *system_memory,
192 ram_addr_t below_4g_mem_size,
193 ram_addr_t above_4g_mem_size,
194 MemoryRegion *rom_memory,
195 MemoryRegion **ram_memory,
196 PcGuestInfo *guest_info);
197 qemu_irq pc_allocate_cpu_irq(void);
198 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
199 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
200 ISADevice **rtc_state,
201 bool create_fdctrl,
202 ISADevice **floppy,
203 bool no_vmport,
204 uint32 hpet_irqs);
205 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
206 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
207 const char *boot_device, MachineState *machine,
208 ISADevice *floppy, BusState *ide0, BusState *ide1,
209 ISADevice *s);
210 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
211 void pc_pci_device_init(PCIBus *pci_bus);
212
213 typedef void (*cpu_set_smm_t)(int smm, void *arg);
214
215 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
216
217 /* acpi_piix.c */
218
219 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
220 qemu_irq sci_irq, qemu_irq smi_irq,
221 int smm_enabled, DeviceState **piix4_pm);
222 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
223
224 /* hpet.c */
225 extern int no_hpet;
226
227 /* piix_pci.c */
228 struct PCII440FXState;
229 typedef struct PCII440FXState PCII440FXState;
230
231 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
232 ISABus **isa_bus, qemu_irq *pic,
233 MemoryRegion *address_space_mem,
234 MemoryRegion *address_space_io,
235 ram_addr_t ram_size,
236 ram_addr_t below_4g_mem_size,
237 ram_addr_t above_4g_mem_size,
238 MemoryRegion *pci_memory,
239 MemoryRegion *ram_memory);
240
241 PCIBus *find_i440fx(void);
242 /* piix4.c */
243 extern PCIDevice *piix4_dev;
244 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
245
246 /* vga.c */
247 enum vga_retrace_method {
248 VGA_RETRACE_DUMB,
249 VGA_RETRACE_PRECISE
250 };
251
252 extern enum vga_retrace_method vga_retrace_method;
253
254 int isa_vga_mm_init(hwaddr vram_base,
255 hwaddr ctrl_base, int it_shift,
256 MemoryRegion *address_space);
257
258 /* ne2000.c */
259 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
260 {
261 DeviceState *dev;
262 ISADevice *isadev;
263
264 qemu_check_nic_model(nd, "ne2k_isa");
265
266 isadev = isa_try_create(bus, "ne2k_isa");
267 if (!isadev) {
268 return false;
269 }
270 dev = DEVICE(isadev);
271 qdev_prop_set_uint32(dev, "iobase", base);
272 qdev_prop_set_uint32(dev, "irq", irq);
273 qdev_set_nic_properties(dev, nd);
274 qdev_init_nofail(dev);
275 return true;
276 }
277
278 /* pc_sysfw.c */
279 void pc_system_firmware_init(MemoryRegion *rom_memory,
280 bool isapc_ram_fw);
281
282 /* pvpanic.c */
283 uint16_t pvpanic_port(void);
284
285 /* e820 types */
286 #define E820_RAM 1
287 #define E820_RESERVED 2
288 #define E820_ACPI 3
289 #define E820_NVS 4
290 #define E820_UNUSABLE 5
291
292 int e820_add_entry(uint64_t, uint64_t, uint32_t);
293 int e820_get_num_entries(void);
294 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
295
296 #define PC_COMPAT_2_3 \
297 HW_COMPAT_2_3
298
299 #define PC_COMPAT_2_2 \
300 PC_COMPAT_2_3 \
301 HW_COMPAT_2_2
302
303 #define PC_COMPAT_2_1 \
304 PC_COMPAT_2_2 \
305 HW_COMPAT_2_1
306
307 #define PC_COMPAT_2_0 \
308 PC_COMPAT_2_1 \
309 {\
310 .driver = "virtio-scsi-pci",\
311 .property = "any_layout",\
312 .value = "off",\
313 },{\
314 .driver = "PIIX4_PM",\
315 .property = "memory-hotplug-support",\
316 .value = "off",\
317 },\
318 {\
319 .driver = "apic",\
320 .property = "version",\
321 .value = stringify(0x11),\
322 },\
323 {\
324 .driver = "nec-usb-xhci",\
325 .property = "superspeed-ports-first",\
326 .value = "off",\
327 },\
328 {\
329 .driver = "nec-usb-xhci",\
330 .property = "force-pcie-endcap",\
331 .value = "on",\
332 },\
333 {\
334 .driver = "pci-serial",\
335 .property = "prog_if",\
336 .value = stringify(0),\
337 },\
338 {\
339 .driver = "pci-serial-2x",\
340 .property = "prog_if",\
341 .value = stringify(0),\
342 },\
343 {\
344 .driver = "pci-serial-4x",\
345 .property = "prog_if",\
346 .value = stringify(0),\
347 },\
348 {\
349 .driver = "virtio-net-pci",\
350 .property = "guest_announce",\
351 .value = "off",\
352 },\
353 {\
354 .driver = "ICH9-LPC",\
355 .property = "memory-hotplug-support",\
356 .value = "off",\
357 },{\
358 .driver = "xio3130-downstream",\
359 .property = COMPAT_PROP_PCP,\
360 .value = "off",\
361 },{\
362 .driver = "ioh3420",\
363 .property = COMPAT_PROP_PCP,\
364 .value = "off",\
365 },
366
367 #define PC_COMPAT_1_7 \
368 PC_COMPAT_2_0 \
369 {\
370 .driver = TYPE_USB_DEVICE,\
371 .property = "msos-desc",\
372 .value = "no",\
373 },\
374 {\
375 .driver = "PIIX4_PM",\
376 .property = "acpi-pci-hotplug-with-bridge-support",\
377 .value = "off",\
378 },\
379 {\
380 .driver = "hpet",\
381 .property = HPET_INTCAP,\
382 .value = stringify(4),\
383 },
384
385 #define PC_COMPAT_1_6 \
386 PC_COMPAT_1_7 \
387 {\
388 .driver = "e1000",\
389 .property = "mitigation",\
390 .value = "off",\
391 },{\
392 .driver = "qemu64-" TYPE_X86_CPU,\
393 .property = "model",\
394 .value = stringify(2),\
395 },{\
396 .driver = "qemu32-" TYPE_X86_CPU,\
397 .property = "model",\
398 .value = stringify(3),\
399 },{\
400 .driver = "i440FX-pcihost",\
401 .property = "short_root_bus",\
402 .value = stringify(1),\
403 },{\
404 .driver = "q35-pcihost",\
405 .property = "short_root_bus",\
406 .value = stringify(1),\
407 },
408
409 #define PC_COMPAT_1_5 \
410 PC_COMPAT_1_6 \
411 {\
412 .driver = "Conroe-" TYPE_X86_CPU,\
413 .property = "model",\
414 .value = stringify(2),\
415 },{\
416 .driver = "Conroe-" TYPE_X86_CPU,\
417 .property = "level",\
418 .value = stringify(2),\
419 },{\
420 .driver = "Penryn-" TYPE_X86_CPU,\
421 .property = "model",\
422 .value = stringify(2),\
423 },{\
424 .driver = "Penryn-" TYPE_X86_CPU,\
425 .property = "level",\
426 .value = stringify(2),\
427 },{\
428 .driver = "Nehalem-" TYPE_X86_CPU,\
429 .property = "model",\
430 .value = stringify(2),\
431 },{\
432 .driver = "Nehalem-" TYPE_X86_CPU,\
433 .property = "level",\
434 .value = stringify(2),\
435 },{\
436 .driver = "virtio-net-pci",\
437 .property = "any_layout",\
438 .value = "off",\
439 },{\
440 .driver = TYPE_X86_CPU,\
441 .property = "pmu",\
442 .value = "on",\
443 },{\
444 .driver = "i440FX-pcihost",\
445 .property = "short_root_bus",\
446 .value = stringify(0),\
447 },{\
448 .driver = "q35-pcihost",\
449 .property = "short_root_bus",\
450 .value = stringify(0),\
451 },
452
453 #define PC_COMPAT_1_4 \
454 PC_COMPAT_1_5 \
455 {\
456 .driver = "scsi-hd",\
457 .property = "discard_granularity",\
458 .value = stringify(0),\
459 },{\
460 .driver = "scsi-cd",\
461 .property = "discard_granularity",\
462 .value = stringify(0),\
463 },{\
464 .driver = "scsi-disk",\
465 .property = "discard_granularity",\
466 .value = stringify(0),\
467 },{\
468 .driver = "ide-hd",\
469 .property = "discard_granularity",\
470 .value = stringify(0),\
471 },{\
472 .driver = "ide-cd",\
473 .property = "discard_granularity",\
474 .value = stringify(0),\
475 },{\
476 .driver = "ide-drive",\
477 .property = "discard_granularity",\
478 .value = stringify(0),\
479 },{\
480 .driver = "virtio-blk-pci",\
481 .property = "discard_granularity",\
482 .value = stringify(0),\
483 },{\
484 .driver = "virtio-serial-pci",\
485 .property = "vectors",\
486 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
487 .value = stringify(0xFFFFFFFF),\
488 },{ \
489 .driver = "virtio-net-pci", \
490 .property = "ctrl_guest_offloads", \
491 .value = "off", \
492 },{\
493 .driver = "e1000",\
494 .property = "romfile",\
495 .value = "pxe-e1000.rom",\
496 },{\
497 .driver = "ne2k_pci",\
498 .property = "romfile",\
499 .value = "pxe-ne2k_pci.rom",\
500 },{\
501 .driver = "pcnet",\
502 .property = "romfile",\
503 .value = "pxe-pcnet.rom",\
504 },{\
505 .driver = "rtl8139",\
506 .property = "romfile",\
507 .value = "pxe-rtl8139.rom",\
508 },{\
509 .driver = "virtio-net-pci",\
510 .property = "romfile",\
511 .value = "pxe-virtio.rom",\
512 },{\
513 .driver = "486-" TYPE_X86_CPU,\
514 .property = "model",\
515 .value = stringify(0),\
516 },
517
518 static inline void pc_common_machine_options(MachineClass *m)
519 {
520 m->default_boot_order = "cad";
521 }
522
523 static inline void pc_default_machine_options(MachineClass *m)
524 {
525 pc_common_machine_options(m);
526 m->hot_add_cpu = pc_hot_add_cpu;
527 m->max_cpus = 255;
528 }
529
530 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
531 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
532 { \
533 MachineClass *mc = MACHINE_CLASS(oc); \
534 optsfn(mc); \
535 mc->name = namestr; \
536 mc->init = initfn; \
537 } \
538 static const TypeInfo pc_machine_type_##suffix = { \
539 .name = namestr TYPE_MACHINE_SUFFIX, \
540 .parent = TYPE_PC_MACHINE, \
541 .class_init = pc_machine_##suffix##_class_init, \
542 }; \
543 static void pc_machine_init_##suffix(void) \
544 { \
545 type_register(&pc_machine_type_##suffix); \
546 } \
547 machine_init(pc_machine_init_##suffix)
548
549 #define SET_MACHINE_COMPAT(m, COMPAT) do { \
550 static GlobalProperty props[] = { \
551 COMPAT \
552 { /* end of list */ } \
553 }; \
554 (m)->compat_props = props; \
555 } while (0)
556
557 #endif