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hw/i386: Make pit a property of common x86 base machine type
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1 #ifndef HW_PC_H
2 #define HW_PC_H
3
4 #include "qemu/notify.h"
5 #include "qapi/qapi-types-common.h"
6 #include "qemu/uuid.h"
7 #include "hw/boards.h"
8 #include "hw/block/fdc.h"
9 #include "hw/block/flash.h"
10 #include "hw/i386/x86.h"
11
12 #include "hw/acpi/acpi_dev_interface.h"
13 #include "hw/hotplug.h"
14 #include "qom/object.h"
15 #include "hw/i386/sgx-epc.h"
16 #include "hw/firmware/smbios.h"
17
18 #define HPET_INTCAP "hpet-intcap"
19
20 /**
21 * PCMachineState:
22 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
23 * @boot_cpus: number of present VCPUs
24 */
25 typedef struct PCMachineState {
26 /*< private >*/
27 X86MachineState parent_obj;
28
29 /* <public> */
30
31 /* State for other subsystems/APIs: */
32 Notifier machine_done;
33
34 /* Pointers to devices and objects: */
35 PCIBus *bus;
36 I2CBus *smbus;
37 PFlashCFI01 *flash[2];
38 ISADevice *pcspk;
39 DeviceState *iommu;
40
41 /* Configuration options: */
42 uint64_t max_ram_below_4g;
43 OnOffAuto vmport;
44 SmbiosEntryPointType smbios_entry_point_type;
45
46 bool acpi_build_enabled;
47 bool smbus_enabled;
48 bool sata_enabled;
49 bool hpet_enabled;
50 bool i8042_enabled;
51 bool default_bus_bypass_iommu;
52 uint64_t max_fw_size;
53
54 /* ACPI Memory hotplug IO base address */
55 hwaddr memhp_io_base;
56
57 SGXEPCState sgx_epc;
58 } PCMachineState;
59
60 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
61 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
62 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
63 #define PC_MACHINE_VMPORT "vmport"
64 #define PC_MACHINE_SMBUS "smbus"
65 #define PC_MACHINE_SATA "sata"
66 #define PC_MACHINE_I8042 "i8042"
67 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size"
68 #define PC_MACHINE_SMBIOS_EP "smbios-entry-point-type"
69
70 /**
71 * PCMachineClass:
72 *
73 * Compat fields:
74 *
75 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
76 * backend's alignment value if provided
77 * @acpi_data_size: Size of the chunk of memory at the top of RAM
78 * for the BIOS ACPI tables and other BIOS
79 * datastructures.
80 * @gigabyte_align: Make sure that guest addresses aligned at
81 * 1Gbyte boundaries get mapped to host
82 * addresses aligned at 1Gbyte boundaries. This
83 * way we can use 1GByte pages in the host.
84 *
85 */
86 struct PCMachineClass {
87 /*< private >*/
88 X86MachineClass parent_class;
89
90 /*< public >*/
91
92 /* Device configuration: */
93 bool pci_enabled;
94 bool kvmclock_enabled;
95 const char *default_nic_model;
96
97 /* Compat options: */
98
99 /* Default CPU model version. See x86_cpu_set_default_version(). */
100 int default_cpu_version;
101
102 /* ACPI compat: */
103 bool has_acpi_build;
104 bool rsdp_in_ram;
105 int legacy_acpi_table_size;
106 unsigned acpi_data_size;
107 bool do_not_add_smb_acpi;
108 int pci_root_uid;
109
110 /* SMBIOS compat: */
111 bool smbios_defaults;
112 bool smbios_legacy_mode;
113 bool smbios_uuid_encoded;
114
115 /* RAM / address space compat: */
116 bool gigabyte_align;
117 bool has_reserved_memory;
118 bool enforce_aligned_dimm;
119 bool broken_reserved_end;
120
121 /* generate legacy CPU hotplug AML */
122 bool legacy_cpu_hotplug;
123
124 /* use PVH to load kernels that support this feature */
125 bool pvh_enabled;
126
127 /* create kvmclock device even when KVM PV features are not exposed */
128 bool kvmclock_create_always;
129 };
130
131 #define TYPE_PC_MACHINE "generic-pc-machine"
132 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE)
133
134 /* ioapic.c */
135
136 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
137
138 /* pc.c */
139 extern int fd_bootchk;
140
141 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
142
143 void pc_guest_info_init(PCMachineState *pcms);
144
145 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
146 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
147 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
148 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
149 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
150 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
151 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
152
153
154 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
155 MemoryRegion *pci_address_space);
156
157 void xen_load_linux(PCMachineState *pcms);
158 void pc_memory_init(PCMachineState *pcms,
159 MemoryRegion *system_memory,
160 MemoryRegion *rom_memory,
161 MemoryRegion **ram_memory);
162 uint64_t pc_pci_hole64_start(void);
163 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
164 void pc_basic_device_init(struct PCMachineState *pcms,
165 ISABus *isa_bus, qemu_irq *gsi,
166 ISADevice **rtc_state,
167 bool create_fdctrl,
168 uint32_t hpet_irqs);
169 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
170 void pc_cmos_init(PCMachineState *pcms,
171 BusState *ide0, BusState *ide1,
172 ISADevice *s);
173 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
174 void pc_pci_device_init(PCIBus *pci_bus);
175
176 typedef void (*cpu_set_smm_t)(int smm, void *arg);
177
178 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
179
180 ISADevice *pc_find_fdc0(void);
181
182 /* port92.c */
183 #define PORT92_A20_LINE "a20"
184
185 #define TYPE_PORT92 "port92"
186
187 /* pc_sysfw.c */
188 void pc_system_flash_create(PCMachineState *pcms);
189 void pc_system_flash_cleanup_unused(PCMachineState *pcms);
190 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
191 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data,
192 int *data_len);
193 void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size);
194
195 /* hw/i386/acpi-common.c */
196 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
197 const CPUArchIdList *apic_ids, GArray *entry,
198 bool force_enabled);
199
200 /* sgx.c */
201 void pc_machine_init_sgx_epc(PCMachineState *pcms);
202
203 extern GlobalProperty pc_compat_7_0[];
204 extern const size_t pc_compat_7_0_len;
205
206 extern GlobalProperty pc_compat_6_2[];
207 extern const size_t pc_compat_6_2_len;
208
209 extern GlobalProperty pc_compat_6_1[];
210 extern const size_t pc_compat_6_1_len;
211
212 extern GlobalProperty pc_compat_6_0[];
213 extern const size_t pc_compat_6_0_len;
214
215 extern GlobalProperty pc_compat_5_2[];
216 extern const size_t pc_compat_5_2_len;
217
218 extern GlobalProperty pc_compat_5_1[];
219 extern const size_t pc_compat_5_1_len;
220
221 extern GlobalProperty pc_compat_5_0[];
222 extern const size_t pc_compat_5_0_len;
223
224 extern GlobalProperty pc_compat_4_2[];
225 extern const size_t pc_compat_4_2_len;
226
227 extern GlobalProperty pc_compat_4_1[];
228 extern const size_t pc_compat_4_1_len;
229
230 extern GlobalProperty pc_compat_4_0[];
231 extern const size_t pc_compat_4_0_len;
232
233 extern GlobalProperty pc_compat_3_1[];
234 extern const size_t pc_compat_3_1_len;
235
236 extern GlobalProperty pc_compat_3_0[];
237 extern const size_t pc_compat_3_0_len;
238
239 extern GlobalProperty pc_compat_2_12[];
240 extern const size_t pc_compat_2_12_len;
241
242 extern GlobalProperty pc_compat_2_11[];
243 extern const size_t pc_compat_2_11_len;
244
245 extern GlobalProperty pc_compat_2_10[];
246 extern const size_t pc_compat_2_10_len;
247
248 extern GlobalProperty pc_compat_2_9[];
249 extern const size_t pc_compat_2_9_len;
250
251 extern GlobalProperty pc_compat_2_8[];
252 extern const size_t pc_compat_2_8_len;
253
254 extern GlobalProperty pc_compat_2_7[];
255 extern const size_t pc_compat_2_7_len;
256
257 extern GlobalProperty pc_compat_2_6[];
258 extern const size_t pc_compat_2_6_len;
259
260 extern GlobalProperty pc_compat_2_5[];
261 extern const size_t pc_compat_2_5_len;
262
263 extern GlobalProperty pc_compat_2_4[];
264 extern const size_t pc_compat_2_4_len;
265
266 extern GlobalProperty pc_compat_2_3[];
267 extern const size_t pc_compat_2_3_len;
268
269 extern GlobalProperty pc_compat_2_2[];
270 extern const size_t pc_compat_2_2_len;
271
272 extern GlobalProperty pc_compat_2_1[];
273 extern const size_t pc_compat_2_1_len;
274
275 extern GlobalProperty pc_compat_2_0[];
276 extern const size_t pc_compat_2_0_len;
277
278 extern GlobalProperty pc_compat_1_7[];
279 extern const size_t pc_compat_1_7_len;
280
281 extern GlobalProperty pc_compat_1_6[];
282 extern const size_t pc_compat_1_6_len;
283
284 extern GlobalProperty pc_compat_1_5[];
285 extern const size_t pc_compat_1_5_len;
286
287 extern GlobalProperty pc_compat_1_4[];
288 extern const size_t pc_compat_1_4_len;
289
290 /* Helper for setting model-id for CPU models that changed model-id
291 * depending on QEMU versions up to QEMU 2.4.
292 */
293 #define PC_CPU_MODEL_IDS(v) \
294 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
295 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
296 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
297
298 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
299 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
300 { \
301 MachineClass *mc = MACHINE_CLASS(oc); \
302 optsfn(mc); \
303 mc->init = initfn; \
304 } \
305 static const TypeInfo pc_machine_type_##suffix = { \
306 .name = namestr TYPE_MACHINE_SUFFIX, \
307 .parent = TYPE_PC_MACHINE, \
308 .class_init = pc_machine_##suffix##_class_init, \
309 }; \
310 static void pc_machine_init_##suffix(void) \
311 { \
312 type_register(&pc_machine_type_##suffix); \
313 } \
314 type_init(pc_machine_init_##suffix)
315
316 #endif