4 #include "qemu-common.h"
5 #include "exec/memory.h"
7 #include "hw/isa/isa.h"
8 #include "hw/block/fdc.h"
10 #include "hw/i386/ioapic.h"
12 #include "qemu/range.h"
13 #include "qemu/bitmap.h"
14 #include "sysemu/sysemu.h"
15 #include "hw/pci/pci.h"
16 #include "hw/mem/pc-dimm.h"
17 #include "hw/mem/nvdimm.h"
18 #include "hw/acpi/acpi_dev_interface.h"
20 #define HPET_INTCAP "hpet-intcap"
24 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
25 * @boot_cpus: number of present VCPUs
27 struct PCMachineState
{
29 MachineState parent_obj
;
33 /* State for other subsystems/APIs: */
34 Notifier machine_done
;
36 /* Pointers to devices and objects: */
37 HotplugHandler
*acpi_dev
;
43 /* Configuration options: */
44 uint64_t max_ram_below_4g
;
48 AcpiNVDIMMState acpi_nvdimm_state
;
50 bool acpi_build_enabled
;
55 /* RAM information (sizes, addresses, configuration): */
56 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
58 /* CPU and apic information: */
59 bool apic_xrupt_override
;
60 unsigned apic_id_limit
;
63 /* NUMA information: */
67 /* Address space used by IOAPIC device. All IOAPIC interrupts
68 * will be translated to MSI messages in the address space. */
69 AddressSpace
*ioapic_as
;
72 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
73 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
74 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
75 #define PC_MACHINE_VMPORT "vmport"
76 #define PC_MACHINE_SMM "smm"
77 #define PC_MACHINE_NVDIMM "nvdimm"
78 #define PC_MACHINE_NVDIMM_PERSIST "nvdimm-persistence"
79 #define PC_MACHINE_SMBUS "smbus"
80 #define PC_MACHINE_SATA "sata"
81 #define PC_MACHINE_PIT "pit"
88 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
89 * backend's alignment value if provided
90 * @acpi_data_size: Size of the chunk of memory at the top of RAM
91 * for the BIOS ACPI tables and other BIOS
93 * @gigabyte_align: Make sure that guest addresses aligned at
94 * 1Gbyte boundaries get mapped to host
95 * addresses aligned at 1Gbyte boundaries. This
96 * way we can use 1GByte pages in the host.
99 struct PCMachineClass
{
101 MachineClass parent_class
;
105 /* Device configuration: */
107 bool kvmclock_enabled
;
108 const char *default_nic_model
;
110 /* Compat options: */
115 int legacy_acpi_table_size
;
116 unsigned acpi_data_size
;
119 bool smbios_defaults
;
120 bool smbios_legacy_mode
;
121 bool smbios_uuid_encoded
;
123 /* RAM / address space compat: */
125 bool has_reserved_memory
;
126 bool enforce_aligned_dimm
;
127 bool broken_reserved_end
;
129 /* TSC rate migration: */
131 /* generate legacy CPU hotplug AML */
132 bool legacy_cpu_hotplug
;
134 /* use DMA capable linuxboot option rom */
135 bool linuxboot_dma_enabled
;
138 #define TYPE_PC_MACHINE "generic-pc-machine"
139 #define PC_MACHINE(obj) \
140 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
141 #define PC_MACHINE_GET_CLASS(obj) \
142 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
143 #define PC_MACHINE_CLASS(klass) \
144 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
148 extern DeviceState
*isa_pic
;
149 qemu_irq
*i8259_init(ISABus
*bus
, qemu_irq parent_irq
);
150 qemu_irq
*kvm_i8259_init(ISABus
*bus
);
151 int pic_read_irq(DeviceState
*d
);
152 int pic_get_output(DeviceState
*d
);
156 /* Global System Interrupts */
158 #define GSI_NUM_PINS IOAPIC_NUM_PINS
160 typedef struct GSIState
{
161 qemu_irq i8259_irq
[ISA_NUM_IRQS
];
162 qemu_irq ioapic_irq
[IOAPIC_NUM_PINS
];
165 void gsi_handler(void *opaque
, int n
, int level
);
168 #define TYPE_VMPORT "vmport"
169 typedef uint32_t (VMPortReadFunc
)(void *opaque
, uint32_t address
);
171 static inline void vmport_init(ISABus
*bus
)
173 isa_create_simple(bus
, TYPE_VMPORT
);
176 void vmport_register(unsigned char command
, VMPortReadFunc
*func
, void *opaque
);
177 void vmmouse_get_data(uint32_t *data
);
178 void vmmouse_set_data(const uint32_t *data
);
181 extern int fd_bootchk
;
183 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
);
184 void pc_register_ferr_irq(qemu_irq irq
);
185 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
);
187 void pc_cpus_init(PCMachineState
*pcms
);
188 void pc_hot_add_cpu(const int64_t id
, Error
**errp
);
189 void pc_acpi_init(const char *default_dsdt
);
191 void pc_guest_info_init(PCMachineState
*pcms
);
193 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
194 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
195 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
196 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
197 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
198 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
199 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
202 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
203 MemoryRegion
*pci_address_space
);
205 void xen_load_linux(PCMachineState
*pcms
);
206 void pc_memory_init(PCMachineState
*pcms
,
207 MemoryRegion
*system_memory
,
208 MemoryRegion
*rom_memory
,
209 MemoryRegion
**ram_memory
);
210 uint64_t pc_pci_hole64_start(void);
211 qemu_irq
pc_allocate_cpu_irq(void);
212 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
);
213 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
214 ISADevice
**rtc_state
,
219 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
);
220 void pc_cmos_init(PCMachineState
*pcms
,
221 BusState
*ide0
, BusState
*ide1
,
223 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
);
224 void pc_pci_device_init(PCIBus
*pci_bus
);
226 typedef void (*cpu_set_smm_t
)(int smm
, void *arg
);
228 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
);
230 ISADevice
*pc_find_fdc0(void);
231 int cmos_get_fd_drive_type(FloppyDriveType fd0
);
233 #define FW_CFG_IO_BASE 0x510
235 #define PORT92_A20_LINE "a20"
239 I2CBus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
240 qemu_irq sci_irq
, qemu_irq smi_irq
,
241 int smm_enabled
, DeviceState
**piix4_pm
);
247 struct PCII440FXState
;
248 typedef struct PCII440FXState PCII440FXState
;
250 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
251 #define TYPE_I440FX_PCI_DEVICE "i440FX"
253 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
256 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
257 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
259 #define RCR_IOPORT 0xcf9
261 PCIBus
*i440fx_init(const char *host_type
, const char *pci_type
,
262 PCII440FXState
**pi440fx_state
, int *piix_devfn
,
263 ISABus
**isa_bus
, qemu_irq
*pic
,
264 MemoryRegion
*address_space_mem
,
265 MemoryRegion
*address_space_io
,
267 ram_addr_t below_4g_mem_size
,
268 ram_addr_t above_4g_mem_size
,
269 MemoryRegion
*pci_memory
,
270 MemoryRegion
*ram_memory
);
272 PCIBus
*find_i440fx(void);
274 extern PCIDevice
*piix4_dev
;
275 int piix4_init(PCIBus
*bus
, ISABus
**isa_bus
, int devfn
);
278 void pc_system_firmware_init(MemoryRegion
*rom_memory
,
282 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
283 const CPUArchIdList
*apic_ids
, GArray
*entry
);
287 #define E820_RESERVED 2
290 #define E820_UNUSABLE 5
292 int e820_add_entry(uint64_t, uint64_t, uint32_t);
293 int e820_get_num_entries(void);
294 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
296 extern GlobalProperty pc_compat_3_1
[];
297 extern const size_t pc_compat_3_1_len
;
299 extern GlobalProperty pc_compat_3_0
[];
300 extern const size_t pc_compat_3_0_len
;
302 extern GlobalProperty pc_compat_2_12
[];
303 extern const size_t pc_compat_2_12_len
;
305 extern GlobalProperty pc_compat_2_11
[];
306 extern const size_t pc_compat_2_11_len
;
308 extern GlobalProperty pc_compat_2_10
[];
309 extern const size_t pc_compat_2_10_len
;
311 extern GlobalProperty pc_compat_2_9
[];
312 extern const size_t pc_compat_2_9_len
;
314 extern GlobalProperty pc_compat_2_8
[];
315 extern const size_t pc_compat_2_8_len
;
317 extern GlobalProperty pc_compat_2_7
[];
318 extern const size_t pc_compat_2_7_len
;
320 extern GlobalProperty pc_compat_2_6
[];
321 extern const size_t pc_compat_2_6_len
;
323 extern GlobalProperty pc_compat_2_5
[];
324 extern const size_t pc_compat_2_5_len
;
326 extern GlobalProperty pc_compat_2_4
[];
327 extern const size_t pc_compat_2_4_len
;
329 extern GlobalProperty pc_compat_2_3
[];
330 extern const size_t pc_compat_2_3_len
;
332 extern GlobalProperty pc_compat_2_2
[];
333 extern const size_t pc_compat_2_2_len
;
335 extern GlobalProperty pc_compat_2_1
[];
336 extern const size_t pc_compat_2_1_len
;
338 extern GlobalProperty pc_compat_2_0
[];
339 extern const size_t pc_compat_2_0_len
;
341 extern GlobalProperty pc_compat_1_7
[];
342 extern const size_t pc_compat_1_7_len
;
344 extern GlobalProperty pc_compat_1_6
[];
345 extern const size_t pc_compat_1_6_len
;
347 extern GlobalProperty pc_compat_1_5
[];
348 extern const size_t pc_compat_1_5_len
;
350 extern GlobalProperty pc_compat_1_4
[];
351 extern const size_t pc_compat_1_4_len
;
353 /* Helper for setting model-id for CPU models that changed model-id
354 * depending on QEMU versions up to QEMU 2.4.
356 #define PC_CPU_MODEL_IDS(v) \
357 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
358 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
359 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
361 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
362 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
364 MachineClass *mc = MACHINE_CLASS(oc); \
368 static const TypeInfo pc_machine_type_##suffix = { \
369 .name = namestr TYPE_MACHINE_SUFFIX, \
370 .parent = TYPE_PC_MACHINE, \
371 .class_init = pc_machine_##suffix##_class_init, \
373 static void pc_machine_init_##suffix(void) \
375 type_register(&pc_machine_type_##suffix); \
377 type_init(pc_machine_init_##suffix)
379 extern void igd_passthrough_isa_bridge_create(PCIBus
*bus
, uint16_t gpu_dev_id
);