4 #include "exec/memory.h"
6 #include "hw/isa/isa.h"
7 #include "hw/block/fdc.h"
8 #include "hw/block/flash.h"
10 #include "hw/i386/ioapic.h"
11 #include "hw/i386/x86.h"
13 #include "qemu/range.h"
14 #include "qemu/bitmap.h"
15 #include "qemu/module.h"
16 #include "hw/pci/pci.h"
17 #include "hw/mem/pc-dimm.h"
18 #include "hw/mem/nvdimm.h"
19 #include "hw/acpi/acpi_dev_interface.h"
21 #define HPET_INTCAP "hpet-intcap"
25 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
26 * @boot_cpus: number of present VCPUs
27 * @smp_dies: number of dies per one package
29 struct PCMachineState
{
31 X86MachineState parent_obj
;
35 /* State for other subsystems/APIs: */
36 Notifier machine_done
;
38 /* Pointers to devices and objects: */
39 HotplugHandler
*acpi_dev
;
42 PFlashCFI01
*flash
[2];
44 /* Configuration options: */
48 bool acpi_build_enabled
;
53 /* NUMA information: */
57 /* ACPI Memory hotplug IO base address */
61 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
62 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
63 #define PC_MACHINE_VMPORT "vmport"
64 #define PC_MACHINE_SMM "smm"
65 #define PC_MACHINE_SMBUS "smbus"
66 #define PC_MACHINE_SATA "sata"
67 #define PC_MACHINE_PIT "pit"
74 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
75 * backend's alignment value if provided
76 * @acpi_data_size: Size of the chunk of memory at the top of RAM
77 * for the BIOS ACPI tables and other BIOS
79 * @gigabyte_align: Make sure that guest addresses aligned at
80 * 1Gbyte boundaries get mapped to host
81 * addresses aligned at 1Gbyte boundaries. This
82 * way we can use 1GByte pages in the host.
85 typedef struct PCMachineClass
{
87 X86MachineClass parent_class
;
91 /* Device configuration: */
93 bool kvmclock_enabled
;
94 const char *default_nic_model
;
98 /* Default CPU model version. See x86_cpu_set_default_version(). */
99 int default_cpu_version
;
104 int legacy_acpi_table_size
;
105 unsigned acpi_data_size
;
106 bool do_not_add_smb_acpi
;
109 bool smbios_defaults
;
110 bool smbios_legacy_mode
;
111 bool smbios_uuid_encoded
;
113 /* RAM / address space compat: */
115 bool has_reserved_memory
;
116 bool enforce_aligned_dimm
;
117 bool broken_reserved_end
;
119 /* TSC rate migration: */
121 /* generate legacy CPU hotplug AML */
122 bool legacy_cpu_hotplug
;
124 /* use DMA capable linuxboot option rom */
125 bool linuxboot_dma_enabled
;
127 /* use PVH to load kernels that support this feature */
131 #define TYPE_PC_MACHINE "generic-pc-machine"
132 #define PC_MACHINE(obj) \
133 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
134 #define PC_MACHINE_GET_CLASS(obj) \
135 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
136 #define PC_MACHINE_CLASS(klass) \
137 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
141 extern DeviceState
*isa_pic
;
142 qemu_irq
*i8259_init(ISABus
*bus
, qemu_irq parent_irq
);
143 qemu_irq
*kvm_i8259_init(ISABus
*bus
);
144 int pic_read_irq(DeviceState
*d
);
145 int pic_get_output(DeviceState
*d
);
149 /* Global System Interrupts */
151 #define GSI_NUM_PINS IOAPIC_NUM_PINS
153 typedef struct GSIState
{
154 qemu_irq i8259_irq
[ISA_NUM_IRQS
];
155 qemu_irq ioapic_irq
[IOAPIC_NUM_PINS
];
158 void gsi_handler(void *opaque
, int n
, int level
);
160 GSIState
*pc_gsi_create(qemu_irq
**irqs
, bool pci_enabled
);
163 #define TYPE_VMPORT "vmport"
164 typedef uint32_t (VMPortReadFunc
)(void *opaque
, uint32_t address
);
166 static inline void vmport_init(ISABus
*bus
)
168 isa_create_simple(bus
, TYPE_VMPORT
);
171 void vmport_register(unsigned char command
, VMPortReadFunc
*func
, void *opaque
);
172 void vmmouse_get_data(uint32_t *data
);
173 void vmmouse_set_data(const uint32_t *data
);
176 extern int fd_bootchk
;
178 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
);
179 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
);
181 void pc_hot_add_cpu(MachineState
*ms
, const int64_t id
, Error
**errp
);
182 void pc_smp_parse(MachineState
*ms
, QemuOpts
*opts
);
184 void pc_guest_info_init(PCMachineState
*pcms
);
186 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
187 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
188 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
189 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
190 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
191 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
192 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
195 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
196 MemoryRegion
*pci_address_space
);
198 void xen_load_linux(PCMachineState
*pcms
);
199 void pc_memory_init(PCMachineState
*pcms
,
200 MemoryRegion
*system_memory
,
201 MemoryRegion
*rom_memory
,
202 MemoryRegion
**ram_memory
);
203 uint64_t pc_pci_hole64_start(void);
204 qemu_irq
pc_allocate_cpu_irq(void);
205 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
);
206 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
207 ISADevice
**rtc_state
,
212 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
);
213 void pc_cmos_init(PCMachineState
*pcms
,
214 BusState
*ide0
, BusState
*ide1
,
216 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
);
217 void pc_pci_device_init(PCIBus
*pci_bus
);
219 typedef void (*cpu_set_smm_t
)(int smm
, void *arg
);
221 void pc_i8259_create(ISABus
*isa_bus
, qemu_irq
*i8259_irqs
);
222 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
);
224 ISADevice
*pc_find_fdc0(void);
225 int cmos_get_fd_drive_type(FloppyDriveType fd0
);
227 #define FW_CFG_IO_BASE 0x510
229 #define PORT92_A20_LINE "a20"
233 I2CBus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
234 qemu_irq sci_irq
, qemu_irq smi_irq
,
235 int smm_enabled
, DeviceState
**piix4_pm
);
241 struct PCII440FXState
;
242 typedef struct PCII440FXState PCII440FXState
;
244 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
245 #define TYPE_I440FX_PCI_DEVICE "i440FX"
247 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
250 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
251 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
253 #define RCR_IOPORT 0xcf9
255 PCIBus
*i440fx_init(const char *host_type
, const char *pci_type
,
256 PCII440FXState
**pi440fx_state
, int *piix_devfn
,
257 ISABus
**isa_bus
, qemu_irq
*pic
,
258 MemoryRegion
*address_space_mem
,
259 MemoryRegion
*address_space_io
,
261 ram_addr_t below_4g_mem_size
,
262 ram_addr_t above_4g_mem_size
,
263 MemoryRegion
*pci_memory
,
264 MemoryRegion
*ram_memory
);
266 PCIBus
*find_i440fx(void);
268 extern PCIDevice
*piix4_dev
;
269 int piix4_init(PCIBus
*bus
, ISABus
**isa_bus
, int devfn
);
272 void pc_system_flash_create(PCMachineState
*pcms
);
273 void pc_system_firmware_init(PCMachineState
*pcms
, MemoryRegion
*rom_memory
);
276 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
277 const CPUArchIdList
*apic_ids
, GArray
*entry
);
279 extern GlobalProperty pc_compat_4_1
[];
280 extern const size_t pc_compat_4_1_len
;
282 extern GlobalProperty pc_compat_4_0
[];
283 extern const size_t pc_compat_4_0_len
;
285 extern GlobalProperty pc_compat_3_1
[];
286 extern const size_t pc_compat_3_1_len
;
288 extern GlobalProperty pc_compat_3_0
[];
289 extern const size_t pc_compat_3_0_len
;
291 extern GlobalProperty pc_compat_2_12
[];
292 extern const size_t pc_compat_2_12_len
;
294 extern GlobalProperty pc_compat_2_11
[];
295 extern const size_t pc_compat_2_11_len
;
297 extern GlobalProperty pc_compat_2_10
[];
298 extern const size_t pc_compat_2_10_len
;
300 extern GlobalProperty pc_compat_2_9
[];
301 extern const size_t pc_compat_2_9_len
;
303 extern GlobalProperty pc_compat_2_8
[];
304 extern const size_t pc_compat_2_8_len
;
306 extern GlobalProperty pc_compat_2_7
[];
307 extern const size_t pc_compat_2_7_len
;
309 extern GlobalProperty pc_compat_2_6
[];
310 extern const size_t pc_compat_2_6_len
;
312 extern GlobalProperty pc_compat_2_5
[];
313 extern const size_t pc_compat_2_5_len
;
315 extern GlobalProperty pc_compat_2_4
[];
316 extern const size_t pc_compat_2_4_len
;
318 extern GlobalProperty pc_compat_2_3
[];
319 extern const size_t pc_compat_2_3_len
;
321 extern GlobalProperty pc_compat_2_2
[];
322 extern const size_t pc_compat_2_2_len
;
324 extern GlobalProperty pc_compat_2_1
[];
325 extern const size_t pc_compat_2_1_len
;
327 extern GlobalProperty pc_compat_2_0
[];
328 extern const size_t pc_compat_2_0_len
;
330 extern GlobalProperty pc_compat_1_7
[];
331 extern const size_t pc_compat_1_7_len
;
333 extern GlobalProperty pc_compat_1_6
[];
334 extern const size_t pc_compat_1_6_len
;
336 extern GlobalProperty pc_compat_1_5
[];
337 extern const size_t pc_compat_1_5_len
;
339 extern GlobalProperty pc_compat_1_4
[];
340 extern const size_t pc_compat_1_4_len
;
342 /* Helper for setting model-id for CPU models that changed model-id
343 * depending on QEMU versions up to QEMU 2.4.
345 #define PC_CPU_MODEL_IDS(v) \
346 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
347 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
348 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
350 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
351 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
353 MachineClass *mc = MACHINE_CLASS(oc); \
357 static const TypeInfo pc_machine_type_##suffix = { \
358 .name = namestr TYPE_MACHINE_SUFFIX, \
359 .parent = TYPE_PC_MACHINE, \
360 .class_init = pc_machine_##suffix##_class_init, \
362 static void pc_machine_init_##suffix(void) \
364 type_register(&pc_machine_type_##suffix); \
366 type_init(pc_machine_init_##suffix)
368 extern void igd_passthrough_isa_bridge_create(PCIBus
*bus
, uint16_t gpu_dev_id
);