include/hw/i386/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "exec/memory.h"
   5 #include "hw/boards.h"
   6 #include "hw/isa/isa.h"
   7 #include "hw/block/fdc.h"
   8 #include "hw/block/flash.h"
   9 #include "net/net.h"
  10 #include "hw/i386/ioapic.h"
  11
  12 #include "qemu/range.h"
  13 #include "qemu/bitmap.h"
  14 #include "qemu/module.h"
  15 #include "hw/pci/pci.h"
  16 #include "hw/mem/pc-dimm.h"
  17 #include "hw/mem/nvdimm.h"
  18 #include "hw/acpi/acpi_dev_interface.h"
  19
  20 #define HPET_INTCAP "hpet-intcap"
  21
  22 /**
  23  * PCMachineState:
  24  * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
  25  * @boot_cpus: number of present VCPUs
  26  * @smp_dies: number of dies per one package
  27  */
  28 struct PCMachineState {
  29     /*< private >*/
  30     MachineState parent_obj;
  31
  32     /* <public> */
  33
  34     /* State for other subsystems/APIs: */
  35     Notifier machine_done;
  36
  37     /* Pointers to devices and objects: */
  38     HotplugHandler *acpi_dev;
  39     ISADevice *rtc;
  40     PCIBus *bus;
  41     I2CBus *smbus;
  42     FWCfgState *fw_cfg;
  43     qemu_irq *gsi;
  44     PFlashCFI01 *flash[2];
  45     GMappedFile *initrd_mapped_file;
  46
  47     /* Configuration options: */
  48     uint64_t max_ram_below_4g;
  49     OnOffAuto vmport;
  50     OnOffAuto smm;
  51
  52     bool acpi_build_enabled;
  53     bool smbus_enabled;
  54     bool sata_enabled;
  55     bool pit_enabled;
  56
  57     /* RAM information (sizes, addresses, configuration): */
  58     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  59
  60     /* CPU and apic information: */
  61     bool apic_xrupt_override;
  62     unsigned apic_id_limit;
  63     uint16_t boot_cpus;
  64     unsigned smp_dies;
  65
  66     /* NUMA information: */
  67     uint64_t numa_nodes;
  68     uint64_t *node_mem;
  69
  70     /* Address space used by IOAPIC device. All IOAPIC interrupts
  71      * will be translated to MSI messages in the address space. */
  72     AddressSpace *ioapic_as;
  73 };
  74
  75 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
  76 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
  77 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
  78 #define PC_MACHINE_VMPORT           "vmport"
  79 #define PC_MACHINE_SMM              "smm"
  80 #define PC_MACHINE_SMBUS            "smbus"
  81 #define PC_MACHINE_SATA             "sata"
  82 #define PC_MACHINE_PIT              "pit"
  83
  84 /**
  85  * PCMachineClass:
  86  *
  87  * Compat fields:
  88  *
  89  * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
  90  *                        backend's alignment value if provided
  91  * @acpi_data_size: Size of the chunk of memory at the top of RAM
  92  *                  for the BIOS ACPI tables and other BIOS
  93  *                  datastructures.
  94  * @gigabyte_align: Make sure that guest addresses aligned at
  95  *                  1Gbyte boundaries get mapped to host
  96  *                  addresses aligned at 1Gbyte boundaries. This
  97  *                  way we can use 1GByte pages in the host.
  98  *
  99  */
 100 typedef struct PCMachineClass {
 101     /*< private >*/
 102     MachineClass parent_class;
 103
 104     /*< public >*/
 105
 106     /* Device configuration: */
 107     bool pci_enabled;
 108     bool kvmclock_enabled;
 109     const char *default_nic_model;
 110
 111     /* Compat options: */
 112
 113     /* Default CPU model version.  See x86_cpu_set_default_version(). */
 114     int default_cpu_version;
 115
 116     /* ACPI compat: */
 117     bool has_acpi_build;
 118     bool rsdp_in_ram;
 119     int legacy_acpi_table_size;
 120     unsigned acpi_data_size;
 121     bool do_not_add_smb_acpi;
 122
 123     /* SMBIOS compat: */
 124     bool smbios_defaults;
 125     bool smbios_legacy_mode;
 126     bool smbios_uuid_encoded;
 127
 128     /* RAM / address space compat: */
 129     bool gigabyte_align;
 130     bool has_reserved_memory;
 131     bool enforce_aligned_dimm;
 132     bool broken_reserved_end;
 133
 134     /* TSC rate migration: */
 135     bool save_tsc_khz;
 136     /* generate legacy CPU hotplug AML */
 137     bool legacy_cpu_hotplug;
 138
 139     /* use DMA capable linuxboot option rom */
 140     bool linuxboot_dma_enabled;
 141
 142     /* use PVH to load kernels that support this feature */
 143     bool pvh_enabled;
 144
 145     /* Enables contiguous-apic-ID mode */
 146     bool compat_apic_id_mode;
 147 } PCMachineClass;
 148
 149 #define TYPE_PC_MACHINE "generic-pc-machine"
 150 #define PC_MACHINE(obj) \
 151     OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
 152 #define PC_MACHINE_GET_CLASS(obj) \
 153     OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
 154 #define PC_MACHINE_CLASS(klass) \
 155     OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
 156
 157 /* i8259.c */
 158
 159 extern DeviceState *isa_pic;
 160 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
 161 qemu_irq *kvm_i8259_init(ISABus *bus);
 162 int pic_read_irq(DeviceState *d);
 163 int pic_get_output(DeviceState *d);
 164
 165 /* ioapic.c */
 166
 167 /* Global System Interrupts */
 168
 169 #define GSI_NUM_PINS IOAPIC_NUM_PINS
 170
 171 typedef struct GSIState {
 172     qemu_irq i8259_irq[ISA_NUM_IRQS];
 173     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 174 } GSIState;
 175
 176 void gsi_handler(void *opaque, int n, int level);
 177
 178 /* vmport.c */
 179 #define TYPE_VMPORT "vmport"
 180 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 181
 182 static inline void vmport_init(ISABus *bus)
 183 {
 184     isa_create_simple(bus, TYPE_VMPORT);
 185 }
 186
 187 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 188 void vmmouse_get_data(uint32_t *data);
 189 void vmmouse_set_data(const uint32_t *data);
 190
 191 /* pc.c */
 192 extern int fd_bootchk;
 193
 194 bool pc_machine_is_smm_enabled(PCMachineState *pcms);
 195 void pc_register_ferr_irq(qemu_irq irq);
 196 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 197
 198 void pc_cpus_init(PCMachineState *pcms);
 199 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
 200 void pc_smp_parse(MachineState *ms, QemuOpts *opts);
 201
 202 void pc_guest_info_init(PCMachineState *pcms);
 203
 204 #define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 205 #define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 206 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 207 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 208 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 209 #define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
 210 #define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
 211
 212
 213 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 214                             MemoryRegion *pci_address_space);
 215
 216 void xen_load_linux(PCMachineState *pcms);
 217 void pc_memory_init(PCMachineState *pcms,
 218                     MemoryRegion *system_memory,
 219                     MemoryRegion *rom_memory,
 220                     MemoryRegion **ram_memory);
 221 uint64_t pc_pci_hole64_start(void);
 222 qemu_irq pc_allocate_cpu_irq(void);
 223 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 224 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 225                           ISADevice **rtc_state,
 226                           bool create_fdctrl,
 227                           bool no_vmport,
 228                           bool has_pit,
 229                           uint32_t hpet_irqs);
 230 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 231 void pc_cmos_init(PCMachineState *pcms,
 232                   BusState *ide0, BusState *ide1,
 233                   ISADevice *s);
 234 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
 235 void pc_pci_device_init(PCIBus *pci_bus);
 236
 237 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 238
 239 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 240
 241 ISADevice *pc_find_fdc0(void);
 242 int cmos_get_fd_drive_type(FloppyDriveType fd0);
 243
 244 #define FW_CFG_IO_BASE     0x510
 245
 246 #define PORT92_A20_LINE "a20"
 247
 248 /* acpi_piix.c */
 249
 250 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 251                       qemu_irq sci_irq, qemu_irq smi_irq,
 252                       int smm_enabled, DeviceState **piix4_pm);
 253
 254 /* hpet.c */
 255 extern int no_hpet;
 256
 257 /* piix_pci.c */
 258 struct PCII440FXState;
 259 typedef struct PCII440FXState PCII440FXState;
 260
 261 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
 262 #define TYPE_I440FX_PCI_DEVICE "i440FX"
 263
 264 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 265
 266 /*
 267  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
 268  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
 269  */
 270 #define RCR_IOPORT 0xcf9
 271
 272 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 273                     PCII440FXState **pi440fx_state, int *piix_devfn,
 274                     ISABus **isa_bus, qemu_irq *pic,
 275                     MemoryRegion *address_space_mem,
 276                     MemoryRegion *address_space_io,
 277                     ram_addr_t ram_size,
 278                     ram_addr_t below_4g_mem_size,
 279                     ram_addr_t above_4g_mem_size,
 280                     MemoryRegion *pci_memory,
 281                     MemoryRegion *ram_memory);
 282
 283 PCIBus *find_i440fx(void);
 284 /* piix4.c */
 285 extern PCIDevice *piix4_dev;
 286 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 287
 288 /* pc_sysfw.c */
 289 void pc_system_flash_create(PCMachineState *pcms);
 290 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
 291
 292 /* acpi-build.c */
 293 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
 294                        const CPUArchIdList *apic_ids, GArray *entry);
 295
 296 extern GlobalProperty pc_compat_4_1[];
 297 extern const size_t pc_compat_4_1_len;
 298
 299 extern GlobalProperty pc_compat_4_0[];
 300 extern const size_t pc_compat_4_0_len;
 301
 302 extern GlobalProperty pc_compat_3_1[];
 303 extern const size_t pc_compat_3_1_len;
 304
 305 extern GlobalProperty pc_compat_3_0[];
 306 extern const size_t pc_compat_3_0_len;
 307
 308 extern GlobalProperty pc_compat_2_12[];
 309 extern const size_t pc_compat_2_12_len;
 310
 311 extern GlobalProperty pc_compat_2_11[];
 312 extern const size_t pc_compat_2_11_len;
 313
 314 extern GlobalProperty pc_compat_2_10[];
 315 extern const size_t pc_compat_2_10_len;
 316
 317 extern GlobalProperty pc_compat_2_9[];
 318 extern const size_t pc_compat_2_9_len;
 319
 320 extern GlobalProperty pc_compat_2_8[];
 321 extern const size_t pc_compat_2_8_len;
 322
 323 extern GlobalProperty pc_compat_2_7[];
 324 extern const size_t pc_compat_2_7_len;
 325
 326 extern GlobalProperty pc_compat_2_6[];
 327 extern const size_t pc_compat_2_6_len;
 328
 329 extern GlobalProperty pc_compat_2_5[];
 330 extern const size_t pc_compat_2_5_len;
 331
 332 extern GlobalProperty pc_compat_2_4[];
 333 extern const size_t pc_compat_2_4_len;
 334
 335 extern GlobalProperty pc_compat_2_3[];
 336 extern const size_t pc_compat_2_3_len;
 337
 338 extern GlobalProperty pc_compat_2_2[];
 339 extern const size_t pc_compat_2_2_len;
 340
 341 extern GlobalProperty pc_compat_2_1[];
 342 extern const size_t pc_compat_2_1_len;
 343
 344 extern GlobalProperty pc_compat_2_0[];
 345 extern const size_t pc_compat_2_0_len;
 346
 347 extern GlobalProperty pc_compat_1_7[];
 348 extern const size_t pc_compat_1_7_len;
 349
 350 extern GlobalProperty pc_compat_1_6[];
 351 extern const size_t pc_compat_1_6_len;
 352
 353 extern GlobalProperty pc_compat_1_5[];
 354 extern const size_t pc_compat_1_5_len;
 355
 356 extern GlobalProperty pc_compat_1_4[];
 357 extern const size_t pc_compat_1_4_len;
 358
 359 /* Helper for setting model-id for CPU models that changed model-id
 360  * depending on QEMU versions up to QEMU 2.4.
 361  */
 362 #define PC_CPU_MODEL_IDS(v) \
 363     { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 364     { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 365     { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
 366
 367 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
 368     static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
 369     { \
 370         MachineClass *mc = MACHINE_CLASS(oc); \
 371         optsfn(mc); \
 372         mc->init = initfn; \
 373     } \
 374     static const TypeInfo pc_machine_type_##suffix = { \
 375         .name       = namestr TYPE_MACHINE_SUFFIX, \
 376         .parent     = TYPE_PC_MACHINE, \
 377         .class_init = pc_machine_##suffix##_class_init, \
 378     }; \
 379     static void pc_machine_init_##suffix(void) \
 380     { \
 381         type_register(&pc_machine_type_##suffix); \
 382     } \
 383     type_init(pc_machine_init_##suffix)
 384
 385 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
 386 #endif