include/hw/i386/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5 #include "exec/memory.h"
   6 #include "hw/isa/isa.h"
   7 #include "hw/block/fdc.h"
   8 #include "net/net.h"
   9 #include "hw/i386/ioapic.h"
  10
  11 #include "qemu/range.h"
  12 #include "qemu/bitmap.h"
  13 #include "sysemu/sysemu.h"
  14 #include "hw/pci/pci.h"
  15
  16 #define HPET_INTCAP "hpet-intcap"
  17
  18 /* PC-style peripherals (also used by other machines).  */
  19
  20 typedef struct PcPciInfo {
  21     Range w32;
  22     Range w64;
  23 } PcPciInfo;
  24
  25 #define ACPI_PM_PROP_S3_DISABLED "disable_s3"
  26 #define ACPI_PM_PROP_S4_DISABLED "disable_s4"
  27 #define ACPI_PM_PROP_S4_VAL "s4_val"
  28 #define ACPI_PM_PROP_SCI_INT "sci_int"
  29 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
  30 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
  31 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
  32 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
  33 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
  34
  35 struct PcGuestInfo {
  36     bool has_pci_info;
  37     bool isapc_ram_fw;
  38     hwaddr ram_size, ram_size_below_4g;
  39     unsigned apic_id_limit;
  40     bool apic_xrupt_override;
  41     uint64_t numa_nodes;
  42     uint64_t *node_mem;
  43     uint64_t *node_cpu;
  44     FWCfgState *fw_cfg;
  45     bool has_acpi_build;
  46 };
  47
  48 /* parallel.c */
  49 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
  50 {
  51     DeviceState *dev;
  52     ISADevice *isadev;
  53
  54     isadev = isa_try_create(bus, "isa-parallel");
  55     if (!isadev) {
  56         return false;
  57     }
  58     dev = DEVICE(isadev);
  59     qdev_prop_set_uint32(dev, "index", index);
  60     qdev_prop_set_chr(dev, "chardev", chr);
  61     if (qdev_init(dev) < 0) {
  62         return false;
  63     }
  64     return true;
  65 }
  66
  67 bool parallel_mm_init(MemoryRegion *address_space,
  68                       hwaddr base, int it_shift, qemu_irq irq,
  69                       CharDriverState *chr);
  70
  71 /* i8259.c */
  72
  73 extern DeviceState *isa_pic;
  74 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
  75 qemu_irq *kvm_i8259_init(ISABus *bus);
  76 int pic_read_irq(DeviceState *d);
  77 int pic_get_output(DeviceState *d);
  78 void pic_info(Monitor *mon, const QDict *qdict);
  79 void irq_info(Monitor *mon, const QDict *qdict);
  80
  81 /* Global System Interrupts */
  82
  83 #define GSI_NUM_PINS IOAPIC_NUM_PINS
  84
  85 typedef struct GSIState {
  86     qemu_irq i8259_irq[ISA_NUM_IRQS];
  87     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
  88 } GSIState;
  89
  90 void gsi_handler(void *opaque, int n, int level);
  91
  92 /* vmport.c */
  93 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
  94
  95 static inline void vmport_init(ISABus *bus)
  96 {
  97     isa_create_simple(bus, "vmport");
  98 }
  99
 100 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 101 void vmmouse_get_data(uint32_t *data);
 102 void vmmouse_set_data(const uint32_t *data);
 103
 104 /* pckbd.c */
 105
 106 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 107 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 108                    MemoryRegion *region, ram_addr_t size,
 109                    hwaddr mask);
 110 void i8042_isa_mouse_fake_event(void *opaque);
 111 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 112
 113 /* pc.c */
 114 extern int fd_bootchk;
 115
 116 void pc_register_ferr_irq(qemu_irq irq);
 117 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 118
 119 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
 120 void pc_hot_add_cpu(const int64_t id, Error **errp);
 121 void pc_acpi_init(const char *default_dsdt);
 122
 123 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
 124                                 ram_addr_t above_4g_mem_size);
 125
 126 #define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 127 #define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 128 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 129 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 130 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 131 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
 132
 133
 134 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 135                             MemoryRegion *pci_address_space);
 136
 137 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
 138                            const char *kernel_filename,
 139                            const char *kernel_cmdline,
 140                            const char *initrd_filename,
 141                            ram_addr_t below_4g_mem_size,
 142                            ram_addr_t above_4g_mem_size,
 143                            MemoryRegion *rom_memory,
 144                            MemoryRegion **ram_memory,
 145                            PcGuestInfo *guest_info);
 146 qemu_irq *pc_allocate_cpu_irq(void);
 147 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 148 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 149                           ISADevice **rtc_state,
 150                           ISADevice **floppy,
 151                           bool no_vmport,
 152                           uint32 hpet_irqs);
 153 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 154 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 155                   const char *boot_device,
 156                   ISADevice *floppy, BusState *ide0, BusState *ide1,
 157                   ISADevice *s);
 158 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
 159 void pc_pci_device_init(PCIBus *pci_bus);
 160
 161 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 162 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 163
 164 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 165
 166 /* acpi_piix.c */
 167
 168 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 169                        qemu_irq sci_irq, qemu_irq smi_irq,
 170                        int kvm_enabled, FWCfgState *fw_cfg);
 171 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 172
 173 /* hpet.c */
 174 extern int no_hpet;
 175
 176 /* piix_pci.c */
 177 struct PCII440FXState;
 178 typedef struct PCII440FXState PCII440FXState;
 179
 180 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
 181                     ISABus **isa_bus, qemu_irq *pic,
 182                     MemoryRegion *address_space_mem,
 183                     MemoryRegion *address_space_io,
 184                     ram_addr_t ram_size,
 185                     ram_addr_t below_4g_mem_size,
 186                     ram_addr_t above_4g_mem_size,
 187                     MemoryRegion *pci_memory,
 188                     MemoryRegion *ram_memory);
 189
 190 PCIBus *find_i440fx(void);
 191 /* piix4.c */
 192 extern PCIDevice *piix4_dev;
 193 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 194
 195 /* vga.c */
 196 enum vga_retrace_method {
 197     VGA_RETRACE_DUMB,
 198     VGA_RETRACE_PRECISE
 199 };
 200
 201 extern enum vga_retrace_method vga_retrace_method;
 202
 203 int isa_vga_mm_init(hwaddr vram_base,
 204                     hwaddr ctrl_base, int it_shift,
 205                     MemoryRegion *address_space);
 206
 207 /* ne2000.c */
 208 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
 209 {
 210     DeviceState *dev;
 211     ISADevice *isadev;
 212
 213     qemu_check_nic_model(nd, "ne2k_isa");
 214
 215     isadev = isa_try_create(bus, "ne2k_isa");
 216     if (!isadev) {
 217         return false;
 218     }
 219     dev = DEVICE(isadev);
 220     qdev_prop_set_uint32(dev, "iobase", base);
 221     qdev_prop_set_uint32(dev, "irq",    irq);
 222     qdev_set_nic_properties(dev, nd);
 223     qdev_init_nofail(dev);
 224     return true;
 225 }
 226
 227 /* pc_sysfw.c */
 228 void pc_system_firmware_init(MemoryRegion *rom_memory,
 229                              bool isapc_ram_fw);
 230
 231 /* pvpanic.c */
 232 uint16_t pvpanic_port(void);
 233
 234 /* e820 types */
 235 #define E820_RAM        1
 236 #define E820_RESERVED   2
 237 #define E820_ACPI       3
 238 #define E820_NVS        4
 239 #define E820_UNUSABLE   5
 240
 241 int e820_add_entry(uint64_t, uint64_t, uint32_t);
 242
 243 #define PC_Q35_COMPAT_1_7 \
 244         PC_COMPAT_1_7, \
 245         {\
 246             .driver   = "hpet",\
 247             .property = HPET_INTCAP,\
 248             .value    = stringify(4),\
 249         }
 250
 251 #define PC_Q35_COMPAT_1_6 \
 252         PC_COMPAT_1_6, \
 253         PC_Q35_COMPAT_1_7
 254
 255 #define PC_Q35_COMPAT_1_5 \
 256         PC_COMPAT_1_5, \
 257         PC_Q35_COMPAT_1_6
 258
 259 #define PC_Q35_COMPAT_1_4 \
 260         PC_COMPAT_1_4, \
 261         PC_Q35_COMPAT_1_5
 262
 263 #define PC_COMPAT_1_7 \
 264         {\
 265             .driver   = TYPE_USB_DEVICE,\
 266             .property = "msos-desc",\
 267             .value    = "no",\
 268         },\
 269         {\
 270             .driver   = "PIIX4_PM",\
 271             .property = "acpi-pci-hotplug-with-bridge-support",\
 272             .value    = "off",\
 273         }
 274
 275 #define PC_COMPAT_1_6 \
 276         PC_COMPAT_1_7, \
 277         {\
 278             .driver   = "e1000",\
 279             .property = "mitigation",\
 280             .value    = "off",\
 281         },{\
 282             .driver   = "qemu64-" TYPE_X86_CPU,\
 283             .property = "model",\
 284             .value    = stringify(2),\
 285         },{\
 286             .driver   = "qemu32-" TYPE_X86_CPU,\
 287             .property = "model",\
 288             .value    = stringify(3),\
 289         },{\
 290             .driver   = "i440FX-pcihost",\
 291             .property = "short_root_bus",\
 292             .value    = stringify(1),\
 293         },{\
 294             .driver   = "q35-pcihost",\
 295             .property = "short_root_bus",\
 296             .value    = stringify(1),\
 297         }
 298
 299 #define PC_COMPAT_1_5 \
 300         PC_COMPAT_1_6, \
 301         {\
 302             .driver   = "Conroe-" TYPE_X86_CPU,\
 303             .property = "model",\
 304             .value    = stringify(2),\
 305         },{\
 306             .driver   = "Conroe-" TYPE_X86_CPU,\
 307             .property = "level",\
 308             .value    = stringify(2),\
 309         },{\
 310             .driver   = "Penryn-" TYPE_X86_CPU,\
 311             .property = "model",\
 312             .value    = stringify(2),\
 313         },{\
 314             .driver   = "Penryn-" TYPE_X86_CPU,\
 315             .property = "level",\
 316             .value    = stringify(2),\
 317         },{\
 318             .driver   = "Nehalem-" TYPE_X86_CPU,\
 319             .property = "model",\
 320             .value    = stringify(2),\
 321         },{\
 322             .driver   = "Nehalem-" TYPE_X86_CPU,\
 323             .property = "level",\
 324             .value    = stringify(2),\
 325         },{\
 326             .driver   = "virtio-net-pci",\
 327             .property = "any_layout",\
 328             .value    = "off",\
 329         },{\
 330             .driver = TYPE_X86_CPU,\
 331             .property = "pmu",\
 332             .value = "on",\
 333         },{\
 334             .driver   = "i440FX-pcihost",\
 335             .property = "short_root_bus",\
 336             .value    = stringify(0),\
 337         },{\
 338             .driver   = "q35-pcihost",\
 339             .property = "short_root_bus",\
 340             .value    = stringify(0),\
 341         }
 342
 343 #define PC_COMPAT_1_4 \
 344         PC_COMPAT_1_5, \
 345         {\
 346             .driver   = "scsi-hd",\
 347             .property = "discard_granularity",\
 348             .value    = stringify(0),\
 349         },{\
 350             .driver   = "scsi-cd",\
 351             .property = "discard_granularity",\
 352             .value    = stringify(0),\
 353         },{\
 354             .driver   = "scsi-disk",\
 355             .property = "discard_granularity",\
 356             .value    = stringify(0),\
 357         },{\
 358             .driver   = "ide-hd",\
 359             .property = "discard_granularity",\
 360             .value    = stringify(0),\
 361         },{\
 362             .driver   = "ide-cd",\
 363             .property = "discard_granularity",\
 364             .value    = stringify(0),\
 365         },{\
 366             .driver   = "ide-drive",\
 367             .property = "discard_granularity",\
 368             .value    = stringify(0),\
 369         },{\
 370             .driver   = "virtio-blk-pci",\
 371             .property = "discard_granularity",\
 372             .value    = stringify(0),\
 373         },{\
 374             .driver   = "virtio-serial-pci",\
 375             .property = "vectors",\
 376             /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
 377             .value    = stringify(0xFFFFFFFF),\
 378         },{ \
 379             .driver   = "virtio-net-pci", \
 380             .property = "ctrl_guest_offloads", \
 381             .value    = "off", \
 382         },{\
 383             .driver   = "e1000",\
 384             .property = "romfile",\
 385             .value    = "pxe-e1000.rom",\
 386         },{\
 387             .driver   = "ne2k_pci",\
 388             .property = "romfile",\
 389             .value    = "pxe-ne2k_pci.rom",\
 390         },{\
 391             .driver   = "pcnet",\
 392             .property = "romfile",\
 393             .value    = "pxe-pcnet.rom",\
 394         },{\
 395             .driver   = "rtl8139",\
 396             .property = "romfile",\
 397             .value    = "pxe-rtl8139.rom",\
 398         },{\
 399             .driver   = "virtio-net-pci",\
 400             .property = "romfile",\
 401             .value    = "pxe-virtio.rom",\
 402         },{\
 403             .driver   = "486-" TYPE_X86_CPU,\
 404             .property = "model",\
 405             .value    = stringify(0),\
 406         }
 407
 408 #define PC_COMMON_MACHINE_OPTIONS \
 409     .default_boot_order = "cad"
 410
 411 #define PC_DEFAULT_MACHINE_OPTIONS \
 412     PC_COMMON_MACHINE_OPTIONS, \
 413     .hot_add_cpu = pc_hot_add_cpu, \
 414     .max_cpus = 255
 415
 416 #endif