include/hw/i386/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "exec/memory.h"
   5 #include "hw/boards.h"
   6 #include "hw/isa/isa.h"
   7 #include "hw/block/fdc.h"
   8 #include "hw/block/flash.h"
   9 #include "net/net.h"
  10 #include "hw/i386/ioapic.h"
  11 #include "hw/i386/x86.h"
  12
  13 #include "qemu/range.h"
  14 #include "qemu/bitmap.h"
  15 #include "qemu/module.h"
  16 #include "hw/pci/pci.h"
  17 #include "hw/mem/pc-dimm.h"
  18 #include "hw/mem/nvdimm.h"
  19 #include "hw/acpi/acpi_dev_interface.h"
  20
  21 #define HPET_INTCAP "hpet-intcap"
  22
  23 /**
  24  * PCMachineState:
  25  * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
  26  * @boot_cpus: number of present VCPUs
  27  * @smp_dies: number of dies per one package
  28  */
  29 struct PCMachineState {
  30     /*< private >*/
  31     X86MachineState parent_obj;
  32
  33     /* <public> */
  34
  35     /* State for other subsystems/APIs: */
  36     Notifier machine_done;
  37
  38     /* Pointers to devices and objects: */
  39     HotplugHandler *acpi_dev;
  40     PCIBus *bus;
  41     I2CBus *smbus;
  42     PFlashCFI01 *flash[2];
  43
  44     /* Configuration options: */
  45     OnOffAuto vmport;
  46     OnOffAuto smm;
  47
  48     bool acpi_build_enabled;
  49     bool smbus_enabled;
  50     bool sata_enabled;
  51     bool pit_enabled;
  52
  53     /* NUMA information: */
  54     uint64_t numa_nodes;
  55     uint64_t *node_mem;
  56
  57     /* ACPI Memory hotplug IO base address */
  58     hwaddr memhp_io_base;
  59 };
  60
  61 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
  62 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
  63 #define PC_MACHINE_VMPORT           "vmport"
  64 #define PC_MACHINE_SMM              "smm"
  65 #define PC_MACHINE_SMBUS            "smbus"
  66 #define PC_MACHINE_SATA             "sata"
  67 #define PC_MACHINE_PIT              "pit"
  68
  69 /**
  70  * PCMachineClass:
  71  *
  72  * Compat fields:
  73  *
  74  * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
  75  *                        backend's alignment value if provided
  76  * @acpi_data_size: Size of the chunk of memory at the top of RAM
  77  *                  for the BIOS ACPI tables and other BIOS
  78  *                  datastructures.
  79  * @gigabyte_align: Make sure that guest addresses aligned at
  80  *                  1Gbyte boundaries get mapped to host
  81  *                  addresses aligned at 1Gbyte boundaries. This
  82  *                  way we can use 1GByte pages in the host.
  83  *
  84  */
  85 typedef struct PCMachineClass {
  86     /*< private >*/
  87     X86MachineClass parent_class;
  88
  89     /*< public >*/
  90
  91     /* Device configuration: */
  92     bool pci_enabled;
  93     bool kvmclock_enabled;
  94     const char *default_nic_model;
  95
  96     /* Compat options: */
  97
  98     /* Default CPU model version.  See x86_cpu_set_default_version(). */
  99     int default_cpu_version;
 100
 101     /* ACPI compat: */
 102     bool has_acpi_build;
 103     bool rsdp_in_ram;
 104     int legacy_acpi_table_size;
 105     unsigned acpi_data_size;
 106     bool do_not_add_smb_acpi;
 107
 108     /* SMBIOS compat: */
 109     bool smbios_defaults;
 110     bool smbios_legacy_mode;
 111     bool smbios_uuid_encoded;
 112
 113     /* RAM / address space compat: */
 114     bool gigabyte_align;
 115     bool has_reserved_memory;
 116     bool enforce_aligned_dimm;
 117     bool broken_reserved_end;
 118
 119     /* generate legacy CPU hotplug AML */
 120     bool legacy_cpu_hotplug;
 121
 122     /* use DMA capable linuxboot option rom */
 123     bool linuxboot_dma_enabled;
 124
 125     /* use PVH to load kernels that support this feature */
 126     bool pvh_enabled;
 127 } PCMachineClass;
 128
 129 #define TYPE_PC_MACHINE "generic-pc-machine"
 130 #define PC_MACHINE(obj) \
 131     OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
 132 #define PC_MACHINE_GET_CLASS(obj) \
 133     OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
 134 #define PC_MACHINE_CLASS(klass) \
 135     OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
 136
 137 /* i8259.c */
 138
 139 extern DeviceState *isa_pic;
 140 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
 141 qemu_irq *kvm_i8259_init(ISABus *bus);
 142 int pic_read_irq(DeviceState *d);
 143 int pic_get_output(DeviceState *d);
 144
 145 /* ioapic.c */
 146
 147 /* Global System Interrupts */
 148
 149 #define GSI_NUM_PINS IOAPIC_NUM_PINS
 150
 151 typedef struct GSIState {
 152     qemu_irq i8259_irq[ISA_NUM_IRQS];
 153     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 154 } GSIState;
 155
 156 void gsi_handler(void *opaque, int n, int level);
 157
 158 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
 159
 160 /* vmport.c */
 161 #define TYPE_VMPORT "vmport"
 162 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 163
 164 static inline void vmport_init(ISABus *bus)
 165 {
 166     isa_create_simple(bus, TYPE_VMPORT);
 167 }
 168
 169 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 170 void vmmouse_get_data(uint32_t *data);
 171 void vmmouse_set_data(const uint32_t *data);
 172
 173 /* pc.c */
 174 extern int fd_bootchk;
 175
 176 bool pc_machine_is_smm_enabled(PCMachineState *pcms);
 177 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 178
 179 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
 180 void pc_smp_parse(MachineState *ms, QemuOpts *opts);
 181
 182 void pc_guest_info_init(PCMachineState *pcms);
 183
 184 #define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 185 #define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 186 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 187 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 188 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 189 #define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
 190 #define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
 191
 192
 193 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 194                             MemoryRegion *pci_address_space);
 195
 196 void xen_load_linux(PCMachineState *pcms);
 197 void pc_memory_init(PCMachineState *pcms,
 198                     MemoryRegion *system_memory,
 199                     MemoryRegion *rom_memory,
 200                     MemoryRegion **ram_memory);
 201 uint64_t pc_pci_hole64_start(void);
 202 qemu_irq pc_allocate_cpu_irq(void);
 203 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 204 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 205                           ISADevice **rtc_state,
 206                           bool create_fdctrl,
 207                           bool no_vmport,
 208                           bool has_pit,
 209                           uint32_t hpet_irqs);
 210 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 211 void pc_cmos_init(PCMachineState *pcms,
 212                   BusState *ide0, BusState *ide1,
 213                   ISADevice *s);
 214 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
 215 void pc_pci_device_init(PCIBus *pci_bus);
 216
 217 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 218
 219 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
 220 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 221
 222 ISADevice *pc_find_fdc0(void);
 223 int cmos_get_fd_drive_type(FloppyDriveType fd0);
 224
 225 #define FW_CFG_IO_BASE     0x510
 226
 227 #define PORT92_A20_LINE "a20"
 228
 229 /* hpet.c */
 230 extern int no_hpet;
 231
 232 /* pc_sysfw.c */
 233 void pc_system_flash_create(PCMachineState *pcms);
 234 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
 235
 236 /* acpi-build.c */
 237 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
 238                        const CPUArchIdList *apic_ids, GArray *entry);
 239
 240 extern GlobalProperty pc_compat_4_2[];
 241 extern const size_t pc_compat_4_2_len;
 242
 243 extern GlobalProperty pc_compat_4_1[];
 244 extern const size_t pc_compat_4_1_len;
 245
 246 extern GlobalProperty pc_compat_4_0[];
 247 extern const size_t pc_compat_4_0_len;
 248
 249 extern GlobalProperty pc_compat_3_1[];
 250 extern const size_t pc_compat_3_1_len;
 251
 252 extern GlobalProperty pc_compat_3_0[];
 253 extern const size_t pc_compat_3_0_len;
 254
 255 extern GlobalProperty pc_compat_2_12[];
 256 extern const size_t pc_compat_2_12_len;
 257
 258 extern GlobalProperty pc_compat_2_11[];
 259 extern const size_t pc_compat_2_11_len;
 260
 261 extern GlobalProperty pc_compat_2_10[];
 262 extern const size_t pc_compat_2_10_len;
 263
 264 extern GlobalProperty pc_compat_2_9[];
 265 extern const size_t pc_compat_2_9_len;
 266
 267 extern GlobalProperty pc_compat_2_8[];
 268 extern const size_t pc_compat_2_8_len;
 269
 270 extern GlobalProperty pc_compat_2_7[];
 271 extern const size_t pc_compat_2_7_len;
 272
 273 extern GlobalProperty pc_compat_2_6[];
 274 extern const size_t pc_compat_2_6_len;
 275
 276 extern GlobalProperty pc_compat_2_5[];
 277 extern const size_t pc_compat_2_5_len;
 278
 279 extern GlobalProperty pc_compat_2_4[];
 280 extern const size_t pc_compat_2_4_len;
 281
 282 extern GlobalProperty pc_compat_2_3[];
 283 extern const size_t pc_compat_2_3_len;
 284
 285 extern GlobalProperty pc_compat_2_2[];
 286 extern const size_t pc_compat_2_2_len;
 287
 288 extern GlobalProperty pc_compat_2_1[];
 289 extern const size_t pc_compat_2_1_len;
 290
 291 extern GlobalProperty pc_compat_2_0[];
 292 extern const size_t pc_compat_2_0_len;
 293
 294 extern GlobalProperty pc_compat_1_7[];
 295 extern const size_t pc_compat_1_7_len;
 296
 297 extern GlobalProperty pc_compat_1_6[];
 298 extern const size_t pc_compat_1_6_len;
 299
 300 extern GlobalProperty pc_compat_1_5[];
 301 extern const size_t pc_compat_1_5_len;
 302
 303 extern GlobalProperty pc_compat_1_4[];
 304 extern const size_t pc_compat_1_4_len;
 305
 306 /* Helper for setting model-id for CPU models that changed model-id
 307  * depending on QEMU versions up to QEMU 2.4.
 308  */
 309 #define PC_CPU_MODEL_IDS(v) \
 310     { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 311     { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 312     { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
 313
 314 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
 315     static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
 316     { \
 317         MachineClass *mc = MACHINE_CLASS(oc); \
 318         optsfn(mc); \
 319         mc->init = initfn; \
 320     } \
 321     static const TypeInfo pc_machine_type_##suffix = { \
 322         .name       = namestr TYPE_MACHINE_SUFFIX, \
 323         .parent     = TYPE_PC_MACHINE, \
 324         .class_init = pc_machine_##suffix##_class_init, \
 325     }; \
 326     static void pc_machine_init_##suffix(void) \
 327     { \
 328         type_register(&pc_machine_type_##suffix); \
 329     } \
 330     type_init(pc_machine_init_##suffix)
 331
 332 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
 333 #endif