include/hw/i386/x86.h

   1 /*
   2  * Copyright (c) 2019 Red Hat, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2 or later, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef HW_I386_X86_H
  18 #define HW_I386_X86_H
  19
  20 #include "exec/hwaddr.h"
  21
  22 #include "hw/boards.h"
  23 #include "hw/intc/ioapic.h"
  24 #include "hw/isa/isa.h"
  25 #include "qom/object.h"
  26
  27 struct X86MachineClass {
  28     /*< private >*/
  29     MachineClass parent;
  30
  31     /*< public >*/
  32
  33     /* TSC rate migration: */
  34     bool save_tsc_khz;
  35     /* use DMA capable linuxboot option rom */
  36     bool fwcfg_dma_enabled;
  37 };
  38
  39 struct X86MachineState {
  40     /*< private >*/
  41     MachineState parent;
  42
  43     /*< public >*/
  44
  45     /* Pointers to devices and objects: */
  46     ISADevice *rtc;
  47     FWCfgState *fw_cfg;
  48     qemu_irq *gsi;
  49     DeviceState *ioapic2;
  50     GMappedFile *initrd_mapped_file;
  51     HotplugHandler *acpi_dev;
  52
  53     /* RAM information (sizes, addresses, configuration): */
  54     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  55
  56     /* Start address of the initial RAM above 4G */
  57     uint64_t above_4g_mem_start;
  58
  59     /* CPU and apic information: */
  60     bool apic_xrupt_override;
  61     unsigned pci_irq_mask;
  62     unsigned apic_id_limit;
  63     uint16_t boot_cpus;
  64     SgxEPCList *sgx_epc_list;
  65
  66     OnOffAuto smm;
  67     OnOffAuto acpi;
  68     OnOffAuto pit;
  69     OnOffAuto pic;
  70
  71     char *oem_id;
  72     char *oem_table_id;
  73     /*
  74      * Address space used by IOAPIC device. All IOAPIC interrupts
  75      * will be translated to MSI messages in the address space.
  76      */
  77     AddressSpace *ioapic_as;
  78
  79     /*
  80      * Ratelimit enforced on detected bus locks in guest.
  81      * The default value of the bus_lock_ratelimit is 0 per second,
  82      * which means no limitation on the guest's bus locks.
  83      */
  84     uint64_t bus_lock_ratelimit;
  85 };
  86
  87 #define X86_MACHINE_SMM              "smm"
  88 #define X86_MACHINE_ACPI             "acpi"
  89 #define X86_MACHINE_PIT              "pit"
  90 #define X86_MACHINE_PIC              "pic"
  91 #define X86_MACHINE_OEM_ID           "x-oem-id"
  92 #define X86_MACHINE_OEM_TABLE_ID     "x-oem-table-id"
  93 #define X86_MACHINE_BUS_LOCK_RATELIMIT  "bus-lock-ratelimit"
  94
  95 #define TYPE_X86_MACHINE   MACHINE_TYPE_NAME("x86")
  96 OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
  97
  98 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
  99                                     unsigned int cpu_index);
 100
 101 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
 102 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
 103 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
 104                                              unsigned cpu_index);
 105 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
 106 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
 107 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx);
 108 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count);
 109 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
 110                       DeviceState *dev, Error **errp);
 111 void x86_cpu_plug(HotplugHandler *hotplug_dev,
 112                   DeviceState *dev, Error **errp);
 113 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
 114                                DeviceState *dev, Error **errp);
 115 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
 116                        DeviceState *dev, Error **errp);
 117
 118 void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
 119                        MemoryRegion *rom_memory, bool isapc_ram_fw);
 120
 121 void x86_load_linux(X86MachineState *x86ms,
 122                     FWCfgState *fw_cfg,
 123                     int acpi_data_size,
 124                     bool pvh_enabled);
 125
 126 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms);
 127 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
 128
 129 /* Global System Interrupts */
 130
 131 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
 132
 133 typedef struct GSIState {
 134     qemu_irq i8259_irq[ISA_NUM_IRQS];
 135     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 136     qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
 137 } GSIState;
 138
 139 qemu_irq x86_allocate_cpu_irq(void);
 140 void gsi_handler(void *opaque, int n, int level);
 141 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 142 DeviceState *ioapic_init_secondary(GSIState *gsi_state);
 143
 144 /* pc_sysfw.c */
 145 void x86_firmware_configure(void *ptr, int size);
 146
 147 #endif