include/hw/intc/arm_gicv3_common.h

   1 /*
   2  * ARM GIC support
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Copyright (c) 2015 Huawei.
   6  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   7  * Written by Peter Maydell
   8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation, either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #ifndef HW_ARM_GICV3_COMMON_H
  25 #define HW_ARM_GICV3_COMMON_H
  26
  27 #include "hw/sysbus.h"
  28 #include "hw/intc/arm_gic_common.h"
  29
  30 /*
  31  * Maximum number of possible interrupts, determined by the GIC architecture.
  32  * Note that this does not include LPIs. When implemented, these should be
  33  * dealt with separately.
  34  */
  35 #define GICV3_MAXIRQ 1020
  36 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
  37
  38 /* Minimum BPR for Secure, or when security not enabled */
  39 #define GIC_MIN_BPR 0
  40 /* Minimum BPR for Nonsecure when security is enabled */
  41 #define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
  42
  43 /* For some distributor fields we want to model the array of 32-bit
  44  * register values which hold various bitmaps corresponding to enabled,
  45  * pending, etc bits. These macros and functions facilitate that; the
  46  * APIs are generally modelled on the generic bitmap.h functions
  47  * (which are unsuitable here because they use 'unsigned long' as the
  48  * underlying storage type, which is very awkward when you need to
  49  * access the data as 32-bit values.)
  50  * Each bitmap contains a bit for each interrupt. Although there is
  51  * space for the PPIs and SGIs, those bits (the first 32) are never
  52  * used as that state lives in the redistributor. The unused bits are
  53  * provided purely so that interrupt X's state is always in bit X; this
  54  * avoids bugs where we forget to subtract GIC_INTERNAL from an
  55  * interrupt number.
  56  */
  57 #define GICV3_BMP_SIZE (DIV_ROUND_UP(GICV3_MAXIRQ, 32))
  58
  59 #define GIC_DECLARE_BITMAP(name) \
  60     uint32_t name[GICV3_BMP_SIZE]
  61
  62 #define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
  63 #define GIC_BIT_WORD(nr) ((nr) / 32)
  64
  65 static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
  66 {
  67     uint32_t mask = GIC_BIT_MASK(nr);
  68     uint32_t *p = addr + GIC_BIT_WORD(nr);
  69
  70     *p |= mask;
  71 }
  72
  73 static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
  74 {
  75     uint32_t mask = GIC_BIT_MASK(nr);
  76     uint32_t *p = addr + GIC_BIT_WORD(nr);
  77
  78     *p &= ~mask;
  79 }
  80
  81 static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
  82 {
  83     return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
  84 }
  85
  86 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
  87 {
  88     uint32_t mask = GIC_BIT_MASK(nr);
  89     uint32_t *p = addr + GIC_BIT_WORD(nr);
  90
  91     *p &= ~mask;
  92     *p |= (val & 1U) << (nr % 32);
  93 }
  94
  95 /* Return a pointer to the 32-bit word containing the specified bit. */
  96 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
  97 {
  98     return addr + GIC_BIT_WORD(nr);
  99 }
 100
 101 typedef struct GICv3State GICv3State;
 102 typedef struct GICv3CPUState GICv3CPUState;
 103
 104 /* Some CPU interface registers come in three flavours:
 105  * Group0, Group1 (Secure) and Group1 (NonSecure)
 106  * (where the latter two are exposed as a single banked system register).
 107  * In the state struct they are implemented as a 3-element array which
 108  * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
 109  * If the CPU doesn't support EL3 then the G1 element is unused.
 110  *
 111  * These constants are also used to communicate the group to use for
 112  * an interrupt or SGI when it is passed between the cpu interface and
 113  * the redistributor or distributor. For those purposes the receiving end
 114  * must be prepared to cope with a Group 1 Secure interrupt even if it does
 115  * not have security support enabled, because security can be disabled
 116  * independently in the CPU and in the GIC. In that case the receiver should
 117  * treat an incoming Group 1 Secure interrupt as if it were Group 0.
 118  * (This architectural requirement is why the _G1 element is the unused one
 119  * in a no-EL3 CPU:  we would otherwise have to translate back and forth
 120  * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
 121  */
 122 #define GICV3_G0 0
 123 #define GICV3_G1 1
 124 #define GICV3_G1NS 2
 125
 126 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
 127  * group-related, so those indices are just 0 for S and 1 for NS.
 128  * (If the CPU or the GIC, respectively, don't support the Security
 129  * extensions then the S element is unused.)
 130  */
 131 #define GICV3_S 0
 132 #define GICV3_NS 1
 133
 134 typedef struct {
 135     int irq;
 136     uint8_t prio;
 137     int grp;
 138 } PendingIrq;
 139
 140 struct GICv3CPUState {
 141     GICv3State *gic;
 142     CPUState *cpu;
 143     qemu_irq parent_irq;
 144     qemu_irq parent_fiq;
 145
 146     /* Redistributor */
 147     uint32_t level;                  /* Current IRQ level */
 148     /* RD_base page registers */
 149     uint32_t gicr_ctlr;
 150     uint64_t gicr_typer;
 151     uint32_t gicr_statusr[2];
 152     uint32_t gicr_waker;
 153     uint64_t gicr_propbaser;
 154     uint64_t gicr_pendbaser;
 155     /* SGI_base page registers */
 156     uint32_t gicr_igroupr0;
 157     uint32_t gicr_ienabler0;
 158     uint32_t gicr_ipendr0;
 159     uint32_t gicr_iactiver0;
 160     uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
 161     uint32_t gicr_igrpmodr0;
 162     uint32_t gicr_nsacr;
 163     uint8_t gicr_ipriorityr[GIC_INTERNAL];
 164
 165     /* CPU interface */
 166     uint64_t icc_ctlr_el1[2];
 167     uint64_t icc_pmr_el1;
 168     uint64_t icc_bpr[3];
 169     uint64_t icc_apr[3][4];
 170     uint64_t icc_igrpen[3];
 171     uint64_t icc_ctlr_el3;
 172
 173     /* Current highest priority pending interrupt for this CPU.
 174      * This is cached information that can be recalculated from the
 175      * real state above; it doesn't need to be migrated.
 176      */
 177     PendingIrq hppi;
 178     /* This is temporary working state, to avoid a malloc in gicv3_update() */
 179     bool seenbetter;
 180 };
 181
 182 struct GICv3State {
 183     /*< private >*/
 184     SysBusDevice parent_obj;
 185     /*< public >*/
 186
 187     MemoryRegion iomem_dist; /* Distributor */
 188     MemoryRegion iomem_redist; /* Redistributors */
 189
 190     uint32_t num_cpu;
 191     uint32_t num_irq;
 192     uint32_t revision;
 193     bool security_extn;
 194     bool irq_reset_nonsecure;
 195
 196     int dev_fd; /* kvm device fd if backed by kvm vgic support */
 197     Error *migration_blocker;
 198
 199     /* Distributor */
 200
 201     /* for a GIC with the security extensions the NS banked version of this
 202      * register is just an alias of bit 1 of the S banked version.
 203      */
 204     uint32_t gicd_ctlr;
 205     uint32_t gicd_statusr[2];
 206     GIC_DECLARE_BITMAP(group);        /* GICD_IGROUPR */
 207     GIC_DECLARE_BITMAP(grpmod);       /* GICD_IGRPMODR */
 208     GIC_DECLARE_BITMAP(enabled);      /* GICD_ISENABLER */
 209     GIC_DECLARE_BITMAP(pending);      /* GICD_ISPENDR */
 210     GIC_DECLARE_BITMAP(active);       /* GICD_ISACTIVER */
 211     GIC_DECLARE_BITMAP(level);        /* Current level */
 212     GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
 213     uint8_t gicd_ipriority[GICV3_MAXIRQ];
 214     uint64_t gicd_irouter[GICV3_MAXIRQ];
 215     /* Cached information: pointer to the cpu i/f for the CPUs specified
 216      * in the IROUTER registers
 217      */
 218     GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
 219     uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
 220
 221     GICv3CPUState *cpu;
 222 };
 223
 224 #define GICV3_BITMAP_ACCESSORS(BMP)                                     \
 225     static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq)   \
 226     {                                                                   \
 227         gic_bmp_set_bit(irq, s->BMP);                                   \
 228     }                                                                   \
 229     static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq)   \
 230     {                                                                   \
 231         return gic_bmp_test_bit(irq, s->BMP);                           \
 232     }                                                                   \
 233     static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
 234     {                                                                   \
 235         gic_bmp_clear_bit(irq, s->BMP);                                 \
 236     }                                                                   \
 237     static inline void gicv3_gicd_##BMP##_replace(GICv3State *s,        \
 238                                                   int irq, int value)   \
 239     {                                                                   \
 240         gic_bmp_replace_bit(irq, s->BMP, value);                        \
 241     }
 242
 243 GICV3_BITMAP_ACCESSORS(group)
 244 GICV3_BITMAP_ACCESSORS(grpmod)
 245 GICV3_BITMAP_ACCESSORS(enabled)
 246 GICV3_BITMAP_ACCESSORS(pending)
 247 GICV3_BITMAP_ACCESSORS(active)
 248 GICV3_BITMAP_ACCESSORS(level)
 249 GICV3_BITMAP_ACCESSORS(edge_trigger)
 250
 251 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
 252 #define ARM_GICV3_COMMON(obj) \
 253      OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
 254 #define ARM_GICV3_COMMON_CLASS(klass) \
 255      OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON)
 256 #define ARM_GICV3_COMMON_GET_CLASS(obj) \
 257      OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
 258
 259 typedef struct ARMGICv3CommonClass {
 260     /*< private >*/
 261     SysBusDeviceClass parent_class;
 262     /*< public >*/
 263
 264     void (*pre_save)(GICv3State *s);
 265     void (*post_load)(GICv3State *s);
 266 } ARMGICv3CommonClass;
 267
 268 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 269                               const MemoryRegionOps *ops);
 270
 271 #endif