include/hw/misc/iotkit-secctl.h

   1 /*
   2  * ARM IoT Kit security controller
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 /* This is a model of the security controller which is part of the
  13  * Arm IoT Kit and documented in
  14  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  15  *
  16  * QEMU interface:
  17  *  + sysbus MMIO region 0 is the "secure privilege control block" registers
  18  *  + sysbus MMIO region 1 is the "non-secure privilege control block" registers
  19  *  + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
  20  *    should RAZ/WI or bus error
  21  *  + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value
  22  * Controlling the 2 APB PPCs in the IoTKit:
  23  *  + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
  24  *  + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
  25  *  + named GPIO outputs apb_ppc{0,1}_irq_enable
  26  *  + named GPIO outputs apb_ppc{0,1}_irq_clear
  27  *  + named GPIO inputs apb_ppc{0,1}_irq_status
  28  * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit
  29  * might provide:
  30  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
  31  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
  32  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
  33  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
  34  *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
  35  * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
  36  * might provide:
  37  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
  38  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
  39  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  40  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  41  *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
  42  * Controlling the MPC in the IoTKit:
  43  *  + named GPIO input mpc_status
  44  * Controlling each of the 16 expansion MPCs which a system using the IoTKit
  45  * might provide:
  46  *  + named GPIO inputs mpcexp_status[0..15]
  47  */
  48
  49 #ifndef IOTKIT_SECCTL_H
  50 #define IOTKIT_SECCTL_H
  51
  52 #include "hw/sysbus.h"
  53
  54 #define TYPE_IOTKIT_SECCTL "iotkit-secctl"
  55 #define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL)
  56
  57 #define IOTS_APB_PPC0_NUM_PORTS 3
  58 #define IOTS_APB_PPC1_NUM_PORTS 1
  59 #define IOTS_PPC_NUM_PORTS 16
  60 #define IOTS_NUM_APB_PPC 2
  61 #define IOTS_NUM_APB_EXP_PPC 4
  62 #define IOTS_NUM_AHB_EXP_PPC 4
  63 #define IOTS_NUM_EXP_MPC 16
  64 #define IOTS_NUM_MPC 1
  65
  66 typedef struct IoTKitSecCtl IoTKitSecCtl;
  67
  68 /* State and IRQ lines relating to a PPC. For the
  69  * PPCs in the IoTKit not all the IRQ lines are used.
  70  */
  71 typedef struct IoTKitSecCtlPPC {
  72     qemu_irq nonsec[IOTS_PPC_NUM_PORTS];
  73     qemu_irq ap[IOTS_PPC_NUM_PORTS];
  74     qemu_irq irq_enable;
  75     qemu_irq irq_clear;
  76
  77     uint32_t ns;
  78     uint32_t sp;
  79     uint32_t nsp;
  80
  81     /* Number of ports actually present */
  82     int numports;
  83     /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */
  84     int irq_bit_offset;
  85     IoTKitSecCtl *parent;
  86 } IoTKitSecCtlPPC;
  87
  88 struct IoTKitSecCtl {
  89     /*< private >*/
  90     SysBusDevice parent_obj;
  91
  92     /*< public >*/
  93     qemu_irq sec_resp_cfg;
  94     qemu_irq nsc_cfg_irq;
  95
  96     MemoryRegion s_regs;
  97     MemoryRegion ns_regs;
  98
  99     uint32_t secppcintstat;
 100     uint32_t secppcinten;
 101     uint32_t secrespcfg;
 102     uint32_t nsccfg;
 103     uint32_t brginten;
 104     uint32_t mpcintstatus;
 105
 106     IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
 107     IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
 108     IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC];
 109 };
 110
 111 #endif