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git.proxmox.com Git - mirror_qemu.git/blob - include/hw/net/imx_fec.h
2 * i.MX FEC/ENET Ethernet Controller emulation.
4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
6 * Based on Coldfire Fast Ethernet Controller emulation.
8 * Copyright (c) 2007 CodeSourcery.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 #include "qom/object.h"
28 #define TYPE_IMX_FEC "imx.fec"
29 typedef struct IMXFECState IMXFECState
;
30 DECLARE_INSTANCE_CHECKER(IMXFECState
, IMX_FEC
,
33 #define TYPE_IMX_ENET "imx.enet"
35 #include "hw/sysbus.h"
74 #define ENET_TDAR1 121
75 #define ENET_TDAR2 123
76 #define ENET_MIIGSK_CFGR 192
77 #define ENET_MIIGSK_ENR 194
80 #define ENET_ATOFF 258
81 #define ENET_ATPER 259
82 #define ENET_ATCOR 260
83 #define ENET_ATINC 261
84 #define ENET_ATSTMP 262
86 #define ENET_TCSR0 386
87 #define ENET_TCCR0 387
88 #define ENET_TCSR1 388
89 #define ENET_TCCR1 389
90 #define ENET_TCSR2 390
91 #define ENET_TCCR2 391
92 #define ENET_TCSR3 392
93 #define ENET_TCCR3 393
98 #define ENET_INT_HB (1 << 31)
99 #define ENET_INT_BABR (1 << 30)
100 #define ENET_INT_BABT (1 << 29)
101 #define ENET_INT_GRA (1 << 28)
102 #define ENET_INT_TXF (1 << 27)
103 #define ENET_INT_TXB (1 << 26)
104 #define ENET_INT_RXF (1 << 25)
105 #define ENET_INT_RXB (1 << 24)
106 #define ENET_INT_MII (1 << 23)
107 #define ENET_INT_EBERR (1 << 22)
108 #define ENET_INT_LC (1 << 21)
109 #define ENET_INT_RL (1 << 20)
110 #define ENET_INT_UN (1 << 19)
111 #define ENET_INT_PLR (1 << 18)
112 #define ENET_INT_WAKEUP (1 << 17)
113 #define ENET_INT_TS_AVAIL (1 << 16)
114 #define ENET_INT_TS_TIMER (1 << 15)
115 #define ENET_INT_TXF2 (1 << 7)
116 #define ENET_INT_TXB2 (1 << 6)
117 #define ENET_INT_TXF1 (1 << 3)
118 #define ENET_INT_TXB1 (1 << 2)
120 #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \
121 ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \
122 ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \
123 ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \
124 ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \
125 ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \
126 ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2)
129 #define ENET_RDAR_RDAR (1 << 24)
132 #define ENET_TDAR_TDAR (1 << 24)
135 #define ENET_ECR_RESET (1 << 0)
136 #define ENET_ECR_ETHEREN (1 << 1)
137 #define ENET_ECR_MAGICEN (1 << 2)
138 #define ENET_ECR_SLEEP (1 << 3)
139 #define ENET_ECR_EN1588 (1 << 4)
140 #define ENET_ECR_SPEED (1 << 5)
141 #define ENET_ECR_DBGEN (1 << 6)
142 #define ENET_ECR_STOPEN (1 << 7)
143 #define ENET_ECR_DSBWP (1 << 8)
146 #define ENET_MIBC_MIB_DIS (1 << 31)
147 #define ENET_MIBC_MIB_IDLE (1 << 30)
148 #define ENET_MIBC_MIB_CLEAR (1 << 29)
151 #define ENET_RCR_LOOP (1 << 0)
152 #define ENET_RCR_DRT (1 << 1)
153 #define ENET_RCR_MII_MODE (1 << 2)
154 #define ENET_RCR_PROM (1 << 3)
155 #define ENET_RCR_BC_REJ (1 << 4)
156 #define ENET_RCR_FCE (1 << 5)
157 #define ENET_RCR_RGMII_EN (1 << 6)
158 #define ENET_RCR_RMII_MODE (1 << 8)
159 #define ENET_RCR_RMII_10T (1 << 9)
160 #define ENET_RCR_PADEN (1 << 12)
161 #define ENET_RCR_PAUFWD (1 << 13)
162 #define ENET_RCR_CRCFWD (1 << 14)
163 #define ENET_RCR_CFEN (1 << 15)
164 #define ENET_RCR_MAX_FL_SHIFT (16)
165 #define ENET_RCR_MAX_FL_LENGTH (14)
166 #define ENET_RCR_NLC (1 << 30)
167 #define ENET_RCR_GRS (1 << 31)
169 #define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH)
172 #define ENET_TCR_GTS (1 << 0)
173 #define ENET_TCR_FDEN (1 << 2)
174 #define ENET_TCR_TFC_PAUSE (1 << 3)
175 #define ENET_TCR_RFC_PAUSE (1 << 4)
176 #define ENET_TCR_ADDSEL_SHIFT (5)
177 #define ENET_TCR_ADDSEL_LENGTH (3)
178 #define ENET_TCR_CRCFWD (1 << 9)
181 #define ENET_TWFR_TFWR_SHIFT (0)
182 #define ENET_TWFR_TFWR_LENGTH (6)
183 #define ENET_TWFR_STRFWD (1 << 8)
185 #define ENET_RACC_SHIFT16 BIT(7)
187 /* Buffer Descriptor. */
194 #define ENET_BD_R (1 << 15)
195 #define ENET_BD_E (1 << 15)
196 #define ENET_BD_O1 (1 << 14)
197 #define ENET_BD_W (1 << 13)
198 #define ENET_BD_O2 (1 << 12)
199 #define ENET_BD_L (1 << 11)
200 #define ENET_BD_TC (1 << 10)
201 #define ENET_BD_ABC (1 << 9)
202 #define ENET_BD_M (1 << 8)
203 #define ENET_BD_BC (1 << 7)
204 #define ENET_BD_MC (1 << 6)
205 #define ENET_BD_LG (1 << 5)
206 #define ENET_BD_NO (1 << 4)
207 #define ENET_BD_CR (1 << 2)
208 #define ENET_BD_OV (1 << 1)
209 #define ENET_BD_TR (1 << 0)
219 uint32_t last_buffer
;
221 uint32_t reserved
[2];
224 #define ENET_BD_ME (1 << 15)
225 #define ENET_BD_TX_INT (1 << 14)
226 #define ENET_BD_TS (1 << 13)
227 #define ENET_BD_PINS (1 << 12)
228 #define ENET_BD_IINS (1 << 11)
229 #define ENET_BD_PE (1 << 10)
230 #define ENET_BD_CE (1 << 9)
231 #define ENET_BD_UC (1 << 8)
232 #define ENET_BD_RX_INT (1 << 7)
234 #define ENET_BD_TXE (1 << 15)
235 #define ENET_BD_UE (1 << 13)
236 #define ENET_BD_EE (1 << 12)
237 #define ENET_BD_FE (1 << 11)
238 #define ENET_BD_LCE (1 << 10)
239 #define ENET_BD_OE (1 << 9)
240 #define ENET_BD_TSE (1 << 8)
241 #define ENET_BD_ICE (1 << 5)
242 #define ENET_BD_PCR (1 << 4)
243 #define ENET_BD_VLAN (1 << 2)
244 #define ENET_BD_IPV6 (1 << 1)
245 #define ENET_BD_FRAG (1 << 0)
247 #define ENET_BD_BDU (1 << 31)
249 #define ENET_TX_RING_NUM 3
251 #define FSL_IMX25_FEC_SIZE 0x4000
255 SysBusDevice parent_obj
;
263 uint32_t regs
[ENET_MAX
];
264 uint32_t rx_descriptor
;
266 uint32_t tx_descriptor
[ENET_TX_RING_NUM
];
267 uint32_t tx_ring_num
;
270 uint32_t phy_control
;
271 uint32_t phy_advertise
;
273 uint32_t phy_int_mask
;
278 /* Buffer used to assemble a Tx frame */
279 uint8_t frame
[ENET_MAX_FRAME_SIZE
];