4 #include "exec/memory.h"
5 #include "sysemu/dma.h"
7 /* PCI includes legacy ISA access. */
8 #include "hw/isa/isa.h"
10 extern bool pci_available
;
14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
15 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
17 #define PCI_FUNC(devfn) ((devfn) & 0x07)
18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
19 #define PCI_BUS_MAX 256
20 #define PCI_DEVFN_MAX 256
21 #define PCI_SLOT_MAX 32
22 #define PCI_FUNC_MAX 8
24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
25 #include "hw/pci/pci_ids.h"
27 /* QEMU-specific Vendor and Device ID definitions */
30 #define PCI_DEVICE_ID_IBM_440GX 0x027f
31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
33 /* Hitachi (0x1054) */
34 #define PCI_VENDOR_ID_HITACHI 0x1054
35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
44 /* Realtek (0x10ec) */
45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
50 /* Marvell (0x11ab) */
51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
53 /* QEMU/Bochs VGA (0x1234) */
54 #define PCI_VENDOR_ID_QEMU 0x1234
55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
56 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112
59 #define PCI_VENDOR_ID_VMWARE 0x15ad
60 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
61 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
62 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
63 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
64 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
65 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
66 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
69 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
70 #define PCI_DEVICE_ID_INTEL_82557 0x1229
71 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
73 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
74 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
75 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
76 #define PCI_SUBDEVICE_ID_QEMU 0x1100
78 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
79 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
80 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
81 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
82 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
83 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
84 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
85 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
86 #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
87 #define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014
88 #define PCI_DEVICE_ID_VIRTIO_MEM 0x1015
90 #define PCI_VENDOR_ID_REDHAT 0x1b36
91 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
92 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
93 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
94 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
95 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
96 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
97 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
98 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
99 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
100 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
101 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
102 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
103 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
104 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
105 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
106 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010
107 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
108 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
109 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
111 #define FMT_PCIBUS PRIx64
113 typedef uint64_t pcibus_t
;
115 struct PCIHostDeviceAddress
{
119 unsigned int function
;
122 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
123 uint32_t address
, uint32_t data
, int len
);
124 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
125 uint32_t address
, int len
);
126 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
127 pcibus_t addr
, pcibus_t size
, int type
);
128 typedef void PCIUnregisterFunc(PCIDevice
*pci_dev
);
130 typedef struct PCIIORegion
{
131 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
132 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
135 MemoryRegion
*memory
;
136 MemoryRegion
*address_space
;
139 #define PCI_ROM_SLOT 6
140 #define PCI_NUM_REGIONS 7
146 QEMU_PCI_VGA_NUM_REGIONS
,
149 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
150 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
151 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
152 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
153 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
154 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
156 #include "hw/pci/pci_regs.h"
157 #include "hw/pci/pcie.h"
159 /* PCI HEADER_TYPE */
160 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
162 /* Size of the standard PCI config header */
163 #define PCI_CONFIG_HEADER_SIZE 0x40
164 /* Size of the standard PCI config space */
165 #define PCI_CONFIG_SPACE_SIZE 0x100
166 /* Size of the standard PCIe config space: 4KB */
167 #define PCIE_CONFIG_SPACE_SIZE 0x1000
169 #define PCI_NUM_PINS 4 /* A-D */
171 /* Bits in cap_present field. */
173 QEMU_PCI_CAP_MSI
= 0x1,
174 QEMU_PCI_CAP_MSIX
= 0x2,
175 QEMU_PCI_CAP_EXPRESS
= 0x4,
177 /* multifunction capable device */
178 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
179 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
181 /* command register SERR bit enabled - unused since QEMU v5.0 */
182 #define QEMU_PCI_CAP_SERR_BITNR 4
183 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
184 /* Standard hot plug controller. */
185 #define QEMU_PCI_SHPC_BITNR 5
186 QEMU_PCI_CAP_SHPC
= (1 << QEMU_PCI_SHPC_BITNR
),
187 #define QEMU_PCI_SLOTID_BITNR 6
188 QEMU_PCI_CAP_SLOTID
= (1 << QEMU_PCI_SLOTID_BITNR
),
189 /* PCI Express capability - Power Controller Present */
190 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
191 QEMU_PCIE_SLTCAP_PCP
= (1 << QEMU_PCIE_SLTCAP_PCP_BITNR
),
192 /* Link active status in endpoint capability is always set */
193 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
194 QEMU_PCIE_LNKSTA_DLLLA
= (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR
),
195 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
196 QEMU_PCIE_EXTCAP_INIT
= (1 << QEMU_PCIE_EXTCAP_INIT_BITNR
),
199 #define TYPE_PCI_DEVICE "pci-device"
200 typedef struct PCIDeviceClass PCIDeviceClass
;
201 DECLARE_OBJ_CHECKERS(PCIDevice
, PCIDeviceClass
,
202 PCI_DEVICE
, TYPE_PCI_DEVICE
)
204 /* Implemented by devices that can be plugged on PCI Express buses */
205 #define INTERFACE_PCIE_DEVICE "pci-express-device"
207 /* Implemented by devices that can be plugged on Conventional PCI buses */
208 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
210 typedef struct PCIINTxRoute
{
219 struct PCIDeviceClass
{
220 DeviceClass parent_class
;
222 void (*realize
)(PCIDevice
*dev
, Error
**errp
);
223 PCIUnregisterFunc
*exit
;
224 PCIConfigReadFunc
*config_read
;
225 PCIConfigWriteFunc
*config_write
;
231 uint16_t subsystem_vendor_id
; /* only for header type = 0 */
232 uint16_t subsystem_id
; /* only for header type = 0 */
235 * pci-to-pci bridge or normal device.
236 * This doesn't mean pci host switch.
237 * When card bus bridge is supported, this would be enhanced.
245 typedef void (*PCIINTxRoutingNotifier
)(PCIDevice
*dev
);
246 typedef int (*MSIVectorUseNotifier
)(PCIDevice
*dev
, unsigned int vector
,
248 typedef void (*MSIVectorReleaseNotifier
)(PCIDevice
*dev
, unsigned int vector
);
249 typedef void (*MSIVectorPollNotifier
)(PCIDevice
*dev
,
250 unsigned int vector_start
,
251 unsigned int vector_end
);
254 PCI_REQ_ID_INVALID
= 0,
256 PCI_REQ_ID_SECONDARY_BUS
,
259 typedef enum PCIReqIDType PCIReqIDType
;
261 struct PCIReqIDCache
{
265 typedef struct PCIReqIDCache PCIReqIDCache
;
269 bool partially_hotplugged
;
272 /* PCI config space */
275 /* Used to enable config checks on load. Note that writable bits are
276 * never checked even if set in cmask. */
279 /* Used to implement R/W bytes */
282 /* Used to implement RW1C(Write 1 to Clear) bytes */
285 /* Used to allocate config space for capabilities. */
288 /* the following fields are read only */
290 /* Cached device to fetch requester ID from, to avoid the PCI
291 * tree walking every time we invoke PCI request (e.g.,
292 * MSI). For conventional PCI root complex, this field is
294 PCIReqIDCache requester_id_cache
;
296 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
297 AddressSpace bus_master_as
;
298 MemoryRegion bus_master_container_region
;
299 MemoryRegion bus_master_enable_region
;
301 /* do not access the following fields */
302 PCIConfigReadFunc
*config_read
;
303 PCIConfigWriteFunc
*config_write
;
305 /* Legacy PCI VGA regions */
306 MemoryRegion
*vga_regions
[QEMU_PCI_VGA_NUM_REGIONS
];
309 /* Current IRQ levels. Used internally by the generic PCI code. */
312 /* Capability bits */
313 uint32_t cap_present
;
315 /* Offset of MSI-X capability in config space */
321 /* Space to store MSIX table & pending bit array */
324 /* MemoryRegion container for msix exclusive BAR setup */
325 MemoryRegion msix_exclusive_bar
;
326 /* Memory Regions for MSIX table and pending bit entries. */
327 MemoryRegion msix_table_mmio
;
328 MemoryRegion msix_pba_mmio
;
329 /* Reference-count for entries actually in use by driver. */
330 unsigned *msix_entry_used
;
331 /* MSIX function mask set or MSIX disabled */
332 bool msix_function_masked
;
333 /* Version id needed for VMState */
336 /* Offset of MSI capability in config space */
340 PCIExpressDevice exp
;
345 /* Location of option rom */
352 /* INTx routing notifier */
353 PCIINTxRoutingNotifier intx_routing_notifier
;
355 /* MSI-X notifiers */
356 MSIVectorUseNotifier msix_vector_use_notifier
;
357 MSIVectorReleaseNotifier msix_vector_release_notifier
;
358 MSIVectorPollNotifier msix_vector_poll_notifier
;
360 /* ID of standby device in net_failover pair */
361 char *failover_pair_id
;
365 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
366 uint8_t attr
, MemoryRegion
*memory
);
367 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
368 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
);
369 void pci_unregister_vga(PCIDevice
*pci_dev
);
370 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
);
372 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
373 uint8_t offset
, uint8_t size
,
376 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
378 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
381 uint32_t pci_default_read_config(PCIDevice
*d
,
382 uint32_t address
, int len
);
383 void pci_default_write_config(PCIDevice
*d
,
384 uint32_t address
, uint32_t val
, int len
);
385 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
386 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
387 MemoryRegion
*pci_address_space(PCIDevice
*dev
);
388 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
);
391 * Should not normally be used by devices. For use by sPAPR target
392 * where QEMU emulates firmware.
394 int pci_bar(PCIDevice
*d
, int reg
);
396 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
397 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
398 typedef PCIINTxRoute (*pci_route_irq_fn
)(void *opaque
, int pin
);
400 #define TYPE_PCI_BUS "PCI"
401 OBJECT_DECLARE_TYPE(PCIBus
, PCIBusClass
, PCI_BUS
)
402 #define TYPE_PCIE_BUS "PCIE"
404 typedef void (*pci_bus_dev_fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
);
405 typedef void (*pci_bus_fn
)(PCIBus
*b
, void *opaque
);
406 typedef void *(*pci_bus_ret_fn
)(PCIBus
*b
, void *opaque
);
408 bool pci_bus_is_express(PCIBus
*bus
);
410 void pci_root_bus_init(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
412 MemoryRegion
*address_space_mem
,
413 MemoryRegion
*address_space_io
,
414 uint8_t devfn_min
, const char *typename
);
415 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
416 MemoryRegion
*address_space_mem
,
417 MemoryRegion
*address_space_io
,
418 uint8_t devfn_min
, const char *typename
);
419 void pci_root_bus_cleanup(PCIBus
*bus
);
420 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
421 void *irq_opaque
, int nirq
);
422 void pci_bus_irqs_cleanup(PCIBus
*bus
);
423 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
);
424 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
425 static inline int pci_swizzle(int slot
, int pin
)
427 return (slot
+ pin
) % PCI_NUM_PINS
;
429 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
);
430 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
431 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
433 MemoryRegion
*address_space_mem
,
434 MemoryRegion
*address_space_io
,
435 uint8_t devfn_min
, int nirq
,
436 const char *typename
);
437 void pci_unregister_root_bus(PCIBus
*bus
);
438 void pci_bus_set_route_irq_fn(PCIBus
*, pci_route_irq_fn
);
439 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
);
440 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new);
441 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
);
442 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
443 PCIINTxRoutingNotifier notifier
);
444 void pci_device_reset(PCIDevice
*dev
);
446 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
447 const char *default_model
,
448 const char *default_devaddr
);
450 PCIDevice
*pci_vga_init(PCIBus
*bus
);
452 static inline PCIBus
*pci_get_bus(const PCIDevice
*dev
)
454 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev
)));
456 int pci_bus_num(PCIBus
*s
);
457 void pci_bus_range(PCIBus
*bus
, int *min_bus
, int *max_bus
);
458 static inline int pci_dev_bus_num(const PCIDevice
*dev
)
460 return pci_bus_num(pci_get_bus(dev
));
463 int pci_bus_numa_node(PCIBus
*bus
);
464 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
467 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
470 void pci_for_each_device_under_bus(PCIBus
*bus
,
471 pci_bus_dev_fn fn
, void *opaque
);
472 void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
475 void pci_for_each_bus_depth_first(PCIBus
*bus
, pci_bus_ret_fn begin
,
476 pci_bus_fn end
, void *parent_state
);
477 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
);
479 /* Use this wrapper when specific scan order is not required. */
481 void pci_for_each_bus(PCIBus
*bus
, pci_bus_fn fn
, void *opaque
)
483 pci_for_each_bus_depth_first(bus
, NULL
, fn
, opaque
);
486 PCIBus
*pci_device_root_bus(const PCIDevice
*d
);
487 const char *pci_root_bus_path(PCIDevice
*dev
);
488 bool pci_bus_bypass_iommu(PCIBus
*bus
);
489 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
);
490 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
);
491 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
);
493 void pci_device_deassert_intx(PCIDevice
*dev
);
495 typedef AddressSpace
*(*PCIIOMMUFunc
)(PCIBus
*, void *, int);
497 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
);
498 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
);
500 pcibus_t
pci_bar_address(PCIDevice
*d
,
501 int reg
, uint8_t type
, pcibus_t size
);
504 pci_set_byte(uint8_t *config
, uint8_t val
)
509 static inline uint8_t
510 pci_get_byte(const uint8_t *config
)
516 pci_set_word(uint8_t *config
, uint16_t val
)
518 stw_le_p(config
, val
);
521 static inline uint16_t
522 pci_get_word(const uint8_t *config
)
524 return lduw_le_p(config
);
528 pci_set_long(uint8_t *config
, uint32_t val
)
530 stl_le_p(config
, val
);
533 static inline uint32_t
534 pci_get_long(const uint8_t *config
)
536 return ldl_le_p(config
);
540 * PCI capabilities and/or their fields
541 * are generally DWORD aligned only so
542 * mechanism used by pci_set/get_quad()
543 * must be tolerant to unaligned pointers
547 pci_set_quad(uint8_t *config
, uint64_t val
)
549 stq_le_p(config
, val
);
552 static inline uint64_t
553 pci_get_quad(const uint8_t *config
)
555 return ldq_le_p(config
);
559 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
561 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
565 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
567 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
571 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
573 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
577 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
579 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
583 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
585 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
589 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
591 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
595 * helper functions to do bit mask operation on configuration space.
596 * Just to set bit, use test-and-set and discard returned value.
597 * Just to clear bit, use test-and-clear and discard returned value.
598 * NOTE: They aren't atomic.
600 static inline uint8_t
601 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
603 uint8_t val
= pci_get_byte(config
);
604 pci_set_byte(config
, val
& ~mask
);
608 static inline uint8_t
609 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
611 uint8_t val
= pci_get_byte(config
);
612 pci_set_byte(config
, val
| mask
);
616 static inline uint16_t
617 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
619 uint16_t val
= pci_get_word(config
);
620 pci_set_word(config
, val
& ~mask
);
624 static inline uint16_t
625 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
627 uint16_t val
= pci_get_word(config
);
628 pci_set_word(config
, val
| mask
);
632 static inline uint32_t
633 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
635 uint32_t val
= pci_get_long(config
);
636 pci_set_long(config
, val
& ~mask
);
640 static inline uint32_t
641 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
643 uint32_t val
= pci_get_long(config
);
644 pci_set_long(config
, val
| mask
);
648 static inline uint64_t
649 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
651 uint64_t val
= pci_get_quad(config
);
652 pci_set_quad(config
, val
& ~mask
);
656 static inline uint64_t
657 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
659 uint64_t val
= pci_get_quad(config
);
660 pci_set_quad(config
, val
| mask
);
664 /* Access a register specified by a mask */
666 pci_set_byte_by_mask(uint8_t *config
, uint8_t mask
, uint8_t reg
)
668 uint8_t val
= pci_get_byte(config
);
669 uint8_t rval
= reg
<< ctz32(mask
);
670 pci_set_byte(config
, (~mask
& val
) | (mask
& rval
));
673 static inline uint8_t
674 pci_get_byte_by_mask(uint8_t *config
, uint8_t mask
)
676 uint8_t val
= pci_get_byte(config
);
677 return (val
& mask
) >> ctz32(mask
);
681 pci_set_word_by_mask(uint8_t *config
, uint16_t mask
, uint16_t reg
)
683 uint16_t val
= pci_get_word(config
);
684 uint16_t rval
= reg
<< ctz32(mask
);
685 pci_set_word(config
, (~mask
& val
) | (mask
& rval
));
688 static inline uint16_t
689 pci_get_word_by_mask(uint8_t *config
, uint16_t mask
)
691 uint16_t val
= pci_get_word(config
);
692 return (val
& mask
) >> ctz32(mask
);
696 pci_set_long_by_mask(uint8_t *config
, uint32_t mask
, uint32_t reg
)
698 uint32_t val
= pci_get_long(config
);
699 uint32_t rval
= reg
<< ctz32(mask
);
700 pci_set_long(config
, (~mask
& val
) | (mask
& rval
));
703 static inline uint32_t
704 pci_get_long_by_mask(uint8_t *config
, uint32_t mask
)
706 uint32_t val
= pci_get_long(config
);
707 return (val
& mask
) >> ctz32(mask
);
711 pci_set_quad_by_mask(uint8_t *config
, uint64_t mask
, uint64_t reg
)
713 uint64_t val
= pci_get_quad(config
);
714 uint64_t rval
= reg
<< ctz32(mask
);
715 pci_set_quad(config
, (~mask
& val
) | (mask
& rval
));
718 static inline uint64_t
719 pci_get_quad_by_mask(uint8_t *config
, uint64_t mask
)
721 uint64_t val
= pci_get_quad(config
);
722 return (val
& mask
) >> ctz32(mask
);
725 PCIDevice
*pci_new_multifunction(int devfn
, bool multifunction
,
727 PCIDevice
*pci_new(int devfn
, const char *name
);
728 bool pci_realize_and_unref(PCIDevice
*dev
, PCIBus
*bus
, Error
**errp
);
730 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
733 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
735 void lsi53c8xx_handle_legacy_cmdline(DeviceState
*lsi_dev
);
737 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
);
738 void pci_set_irq(PCIDevice
*pci_dev
, int level
);
740 static inline int pci_intx(PCIDevice
*pci_dev
)
742 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
745 static inline void pci_irq_assert(PCIDevice
*pci_dev
)
747 pci_set_irq(pci_dev
, 1);
750 static inline void pci_irq_deassert(PCIDevice
*pci_dev
)
752 pci_set_irq(pci_dev
, 0);
756 * FIXME: PCI does not work this way.
757 * All the callers to this method should be fixed.
759 static inline void pci_irq_pulse(PCIDevice
*pci_dev
)
761 pci_irq_assert(pci_dev
);
762 pci_irq_deassert(pci_dev
);
765 static inline int pci_is_express(const PCIDevice
*d
)
767 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
770 static inline int pci_is_express_downstream_port(const PCIDevice
*d
)
774 if (!pci_is_express(d
) || !d
->exp
.exp_cap
) {
778 type
= pcie_cap_get_type(d
);
780 return type
== PCI_EXP_TYPE_DOWNSTREAM
|| type
== PCI_EXP_TYPE_ROOT_PORT
;
783 static inline int pci_is_vf(const PCIDevice
*d
)
785 return d
->exp
.sriov_vf
.pf
!= NULL
;
788 static inline uint32_t pci_config_size(const PCIDevice
*d
)
790 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;
793 static inline uint16_t pci_get_bdf(PCIDevice
*dev
)
795 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev
)), dev
->devfn
);
798 uint16_t pci_requester_id(PCIDevice
*dev
);
800 /* DMA access functions */
801 static inline AddressSpace
*pci_get_address_space(PCIDevice
*dev
)
803 return &dev
->bus_master_as
;
807 * pci_dma_rw: Read from or write to an address space from PCI device.
809 * Return a MemTxResult indicating whether the operation succeeded
810 * or failed (eg unassigned memory, device rejected the transaction,
813 * @dev: #PCIDevice doing the memory access
814 * @addr: address within the #PCIDevice address space
815 * @buf: buffer with the data transferred
816 * @len: the number of bytes to read or write
817 * @dir: indicates the transfer direction
819 static inline MemTxResult
pci_dma_rw(PCIDevice
*dev
, dma_addr_t addr
,
820 void *buf
, dma_addr_t len
,
821 DMADirection dir
, MemTxAttrs attrs
)
823 return dma_memory_rw(pci_get_address_space(dev
), addr
, buf
, len
,
828 * pci_dma_read: Read from an address space from PCI device.
830 * Return a MemTxResult indicating whether the operation succeeded
831 * or failed (eg unassigned memory, device rejected the transaction,
832 * IOMMU fault). Called within RCU critical section.
834 * @dev: #PCIDevice doing the memory access
835 * @addr: address within the #PCIDevice address space
836 * @buf: buffer with the data transferred
837 * @len: length of the data transferred
839 static inline MemTxResult
pci_dma_read(PCIDevice
*dev
, dma_addr_t addr
,
840 void *buf
, dma_addr_t len
)
842 return pci_dma_rw(dev
, addr
, buf
, len
,
843 DMA_DIRECTION_TO_DEVICE
, MEMTXATTRS_UNSPECIFIED
);
847 * pci_dma_write: Write to address space from PCI device.
849 * Return a MemTxResult indicating whether the operation succeeded
850 * or failed (eg unassigned memory, device rejected the transaction,
853 * @dev: #PCIDevice doing the memory access
854 * @addr: address within the #PCIDevice address space
855 * @buf: buffer with the data transferred
856 * @len: the number of bytes to write
858 static inline MemTxResult
pci_dma_write(PCIDevice
*dev
, dma_addr_t addr
,
859 const void *buf
, dma_addr_t len
)
861 return pci_dma_rw(dev
, addr
, (void *) buf
, len
,
862 DMA_DIRECTION_FROM_DEVICE
, MEMTXATTRS_UNSPECIFIED
);
865 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
866 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
868 uint##_bits##_t *val, \
871 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
873 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
875 uint##_bits##_t val, \
878 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
881 PCI_DMA_DEFINE_LDST(ub
, b
, 8);
882 PCI_DMA_DEFINE_LDST(uw_le
, w_le
, 16)
883 PCI_DMA_DEFINE_LDST(l_le
, l_le
, 32);
884 PCI_DMA_DEFINE_LDST(q_le
, q_le
, 64);
885 PCI_DMA_DEFINE_LDST(uw_be
, w_be
, 16)
886 PCI_DMA_DEFINE_LDST(l_be
, l_be
, 32);
887 PCI_DMA_DEFINE_LDST(q_be
, q_be
, 64);
889 #undef PCI_DMA_DEFINE_LDST
892 * pci_dma_map: Map device PCI address space range into host virtual address
893 * @dev: #PCIDevice to be accessed
894 * @addr: address within that device's address space
895 * @plen: pointer to length of buffer; updated on return to indicate
896 * if only a subset of the requested range has been mapped
897 * @dir: indicates the transfer direction
899 * Return: A host pointer, or %NULL if the resources needed to
900 * perform the mapping are exhausted (in that case *@plen
903 static inline void *pci_dma_map(PCIDevice
*dev
, dma_addr_t addr
,
904 dma_addr_t
*plen
, DMADirection dir
)
908 buf
= dma_memory_map(pci_get_address_space(dev
), addr
, plen
, dir
,
909 MEMTXATTRS_UNSPECIFIED
);
913 static inline void pci_dma_unmap(PCIDevice
*dev
, void *buffer
, dma_addr_t len
,
914 DMADirection dir
, dma_addr_t access_len
)
916 dma_memory_unmap(pci_get_address_space(dev
), buffer
, len
, dir
, access_len
);
919 static inline void pci_dma_sglist_init(QEMUSGList
*qsg
, PCIDevice
*dev
,
922 qemu_sglist_init(qsg
, DEVICE(dev
), alloc_hint
, pci_get_address_space(dev
));
925 extern const VMStateDescription vmstate_pci_device
;
927 #define VMSTATE_PCI_DEVICE(_field, _state) { \
928 .name = (stringify(_field)), \
929 .size = sizeof(PCIDevice), \
930 .vmsd = &vmstate_pci_device, \
931 .flags = VMS_STRUCT, \
932 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
935 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
936 .name = (stringify(_field)), \
937 .size = sizeof(PCIDevice), \
938 .vmsd = &vmstate_pci_device, \
939 .flags = VMS_STRUCT|VMS_POINTER, \
940 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
943 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
);
944 void pci_set_power(PCIDevice
*pci_dev
, bool state
);