5 #include "exec/memory.h"
6 #include "sysemu/dma.h"
8 /* PCI includes legacy ISA access. */
9 #include "hw/isa/isa.h"
11 #include "hw/pci/pcie.h"
15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
17 #define PCI_FUNC(devfn) ((devfn) & 0x07)
18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
19 #define PCI_SLOT_MAX 32
20 #define PCI_FUNC_MAX 8
22 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
23 #include "hw/pci/pci_ids.h"
25 /* QEMU-specific Vendor and Device ID definitions */
28 #define PCI_DEVICE_ID_IBM_440GX 0x027f
29 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
31 /* Hitachi (0x1054) */
32 #define PCI_VENDOR_ID_HITACHI 0x1054
33 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
36 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
37 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
38 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
39 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
40 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
42 /* Realtek (0x10ec) */
43 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
46 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
48 /* Marvell (0x11ab) */
49 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
51 /* QEMU/Bochs VGA (0x1234) */
52 #define PCI_VENDOR_ID_QEMU 0x1234
53 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
56 #define PCI_VENDOR_ID_VMWARE 0x15ad
57 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
58 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
59 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
60 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
61 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
63 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
66 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
67 #define PCI_DEVICE_ID_INTEL_82557 0x1229
68 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
70 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
71 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
73 #define PCI_SUBDEVICE_ID_QEMU 0x1100
75 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
76 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
77 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
78 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
79 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
80 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
81 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
83 #define PCI_VENDOR_ID_REDHAT 0x1b36
84 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
85 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
86 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
87 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
88 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
89 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
90 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
91 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
92 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
93 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
94 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
95 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
97 #define FMT_PCIBUS PRIx64
99 typedef uint64_t pcibus_t
;
101 struct PCIHostDeviceAddress
{
105 unsigned int function
;
108 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
109 uint32_t address
, uint32_t data
, int len
);
110 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
111 uint32_t address
, int len
);
112 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
113 pcibus_t addr
, pcibus_t size
, int type
);
114 typedef void PCIUnregisterFunc(PCIDevice
*pci_dev
);
116 typedef struct PCIIORegion
{
117 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
118 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
121 MemoryRegion
*memory
;
122 MemoryRegion
*address_space
;
125 #define PCI_ROM_SLOT 6
126 #define PCI_NUM_REGIONS 7
132 QEMU_PCI_VGA_NUM_REGIONS
,
135 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
136 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
137 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
138 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
139 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
140 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
142 #include "hw/pci/pci_regs.h"
144 /* PCI HEADER_TYPE */
145 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
147 /* Size of the standard PCI config header */
148 #define PCI_CONFIG_HEADER_SIZE 0x40
149 /* Size of the standard PCI config space */
150 #define PCI_CONFIG_SPACE_SIZE 0x100
151 /* Size of the standard PCIe config space: 4KB */
152 #define PCIE_CONFIG_SPACE_SIZE 0x1000
154 #define PCI_NUM_PINS 4 /* A-D */
156 /* Bits in cap_present field. */
158 QEMU_PCI_CAP_MSI
= 0x1,
159 QEMU_PCI_CAP_MSIX
= 0x2,
160 QEMU_PCI_CAP_EXPRESS
= 0x4,
162 /* multifunction capable device */
163 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
164 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
166 /* command register SERR bit enabled */
167 #define QEMU_PCI_CAP_SERR_BITNR 4
168 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
169 /* Standard hot plug controller. */
170 #define QEMU_PCI_SHPC_BITNR 5
171 QEMU_PCI_CAP_SHPC
= (1 << QEMU_PCI_SHPC_BITNR
),
172 #define QEMU_PCI_SLOTID_BITNR 6
173 QEMU_PCI_CAP_SLOTID
= (1 << QEMU_PCI_SLOTID_BITNR
),
174 /* PCI Express capability - Power Controller Present */
175 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
176 QEMU_PCIE_SLTCAP_PCP
= (1 << QEMU_PCIE_SLTCAP_PCP_BITNR
),
179 #define TYPE_PCI_DEVICE "pci-device"
180 #define PCI_DEVICE(obj) \
181 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
182 #define PCI_DEVICE_CLASS(klass) \
183 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
184 #define PCI_DEVICE_GET_CLASS(obj) \
185 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
187 typedef struct PCIINTxRoute
{
196 typedef struct PCIDeviceClass
{
197 DeviceClass parent_class
;
199 void (*realize
)(PCIDevice
*dev
, Error
**errp
);
200 int (*init
)(PCIDevice
*dev
);/* TODO convert to realize() and remove */
201 PCIUnregisterFunc
*exit
;
202 PCIConfigReadFunc
*config_read
;
203 PCIConfigWriteFunc
*config_write
;
209 uint16_t subsystem_vendor_id
; /* only for header type = 0 */
210 uint16_t subsystem_id
; /* only for header type = 0 */
213 * pci-to-pci bridge or normal device.
214 * This doesn't mean pci host switch.
215 * When card bus bridge is supported, this would be enhanced.
220 int is_express
; /* is this device pci express? */
226 typedef void (*PCIINTxRoutingNotifier
)(PCIDevice
*dev
);
227 typedef int (*MSIVectorUseNotifier
)(PCIDevice
*dev
, unsigned int vector
,
229 typedef void (*MSIVectorReleaseNotifier
)(PCIDevice
*dev
, unsigned int vector
);
230 typedef void (*MSIVectorPollNotifier
)(PCIDevice
*dev
,
231 unsigned int vector_start
,
232 unsigned int vector_end
);
235 PCI_REQ_ID_INVALID
= 0,
237 PCI_REQ_ID_SECONDARY_BUS
,
240 typedef enum PCIReqIDType PCIReqIDType
;
242 struct PCIReqIDCache
{
246 typedef struct PCIReqIDCache PCIReqIDCache
;
251 /* PCI config space */
254 /* Used to enable config checks on load. Note that writable bits are
255 * never checked even if set in cmask. */
258 /* Used to implement R/W bytes */
261 /* Used to implement RW1C(Write 1 to Clear) bytes */
264 /* Used to allocate config space for capabilities. */
267 /* the following fields are read only */
270 /* Cached device to fetch requester ID from, to avoid the PCI
271 * tree walking every time we invoke PCI request (e.g.,
272 * MSI). For conventional PCI root complex, this field is
274 PCIReqIDCache requester_id_cache
;
276 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
277 AddressSpace bus_master_as
;
278 MemoryRegion bus_master_enable_region
;
280 /* do not access the following fields */
281 PCIConfigReadFunc
*config_read
;
282 PCIConfigWriteFunc
*config_write
;
284 /* Legacy PCI VGA regions */
285 MemoryRegion
*vga_regions
[QEMU_PCI_VGA_NUM_REGIONS
];
288 /* Current IRQ levels. Used internally by the generic PCI code. */
291 /* Capability bits */
292 uint32_t cap_present
;
294 /* Offset of MSI-X capability in config space */
300 /* Space to store MSIX table & pending bit array */
303 /* MemoryRegion container for msix exclusive BAR setup */
304 MemoryRegion msix_exclusive_bar
;
305 /* Memory Regions for MSIX table and pending bit entries. */
306 MemoryRegion msix_table_mmio
;
307 MemoryRegion msix_pba_mmio
;
308 /* Reference-count for entries actually in use by driver. */
309 unsigned *msix_entry_used
;
310 /* MSIX function mask set or MSIX disabled */
311 bool msix_function_masked
;
312 /* Version id needed for VMState */
315 /* Offset of MSI capability in config space */
319 PCIExpressDevice exp
;
324 /* Location of option rom */
330 /* INTx routing notifier */
331 PCIINTxRoutingNotifier intx_routing_notifier
;
333 /* MSI-X notifiers */
334 MSIVectorUseNotifier msix_vector_use_notifier
;
335 MSIVectorReleaseNotifier msix_vector_release_notifier
;
336 MSIVectorPollNotifier msix_vector_poll_notifier
;
339 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
340 uint8_t attr
, MemoryRegion
*memory
);
341 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
342 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
);
343 void pci_unregister_vga(PCIDevice
*pci_dev
);
344 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
);
346 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
347 uint8_t offset
, uint8_t size
);
348 int pci_add_capability2(PCIDevice
*pdev
, uint8_t cap_id
,
349 uint8_t offset
, uint8_t size
,
352 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
354 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
357 uint32_t pci_default_read_config(PCIDevice
*d
,
358 uint32_t address
, int len
);
359 void pci_default_write_config(PCIDevice
*d
,
360 uint32_t address
, uint32_t val
, int len
);
361 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
362 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
363 MemoryRegion
*pci_address_space(PCIDevice
*dev
);
364 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
);
367 * Should not normally be used by devices. For use by sPAPR target
368 * where QEMU emulates firmware.
370 int pci_bar(PCIDevice
*d
, int reg
);
372 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
373 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
374 typedef PCIINTxRoute (*pci_route_irq_fn
)(void *opaque
, int pin
);
376 #define TYPE_PCI_BUS "PCI"
377 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
378 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
379 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
380 #define TYPE_PCIE_BUS "PCIE"
382 bool pci_bus_is_express(PCIBus
*bus
);
383 bool pci_bus_is_root(PCIBus
*bus
);
384 void pci_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
386 MemoryRegion
*address_space_mem
,
387 MemoryRegion
*address_space_io
,
388 uint8_t devfn_min
, const char *typename
);
389 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
390 MemoryRegion
*address_space_mem
,
391 MemoryRegion
*address_space_io
,
392 uint8_t devfn_min
, const char *typename
);
393 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
394 void *irq_opaque
, int nirq
);
395 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
);
396 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
397 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
);
398 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
399 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
401 MemoryRegion
*address_space_mem
,
402 MemoryRegion
*address_space_io
,
403 uint8_t devfn_min
, int nirq
, const char *typename
);
404 void pci_bus_set_route_irq_fn(PCIBus
*, pci_route_irq_fn
);
405 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
);
406 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new);
407 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
);
408 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
409 PCIINTxRoutingNotifier notifier
);
410 void pci_device_reset(PCIDevice
*dev
);
412 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
413 const char *default_model
,
414 const char *default_devaddr
);
416 PCIDevice
*pci_vga_init(PCIBus
*bus
);
418 int pci_bus_num(PCIBus
*s
);
419 int pci_bus_numa_node(PCIBus
*bus
);
420 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
421 void (*fn
)(PCIBus
*bus
, PCIDevice
*d
, void *opaque
),
423 void pci_for_each_bus_depth_first(PCIBus
*bus
,
424 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
425 void (*end
)(PCIBus
*bus
, void *state
),
427 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
);
429 /* Use this wrapper when specific scan order is not required. */
431 void pci_for_each_bus(PCIBus
*bus
,
432 void (*fn
)(PCIBus
*bus
, void *opaque
),
435 pci_for_each_bus_depth_first(bus
, NULL
, fn
, opaque
);
438 PCIBus
*pci_find_primary_bus(void);
439 PCIBus
*pci_device_root_bus(const PCIDevice
*d
);
440 const char *pci_root_bus_path(PCIDevice
*dev
);
441 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
);
442 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
);
443 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
);
445 void pci_device_deassert_intx(PCIDevice
*dev
);
447 typedef AddressSpace
*(*PCIIOMMUFunc
)(PCIBus
*, void *, int);
449 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
);
450 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
);
453 pci_set_byte(uint8_t *config
, uint8_t val
)
458 static inline uint8_t
459 pci_get_byte(const uint8_t *config
)
465 pci_set_word(uint8_t *config
, uint16_t val
)
467 stw_le_p(config
, val
);
470 static inline uint16_t
471 pci_get_word(const uint8_t *config
)
473 return lduw_le_p(config
);
477 pci_set_long(uint8_t *config
, uint32_t val
)
479 stl_le_p(config
, val
);
482 static inline uint32_t
483 pci_get_long(const uint8_t *config
)
485 return ldl_le_p(config
);
489 * PCI capabilities and/or their fields
490 * are generally DWORD aligned only so
491 * mechanism used by pci_set/get_quad()
492 * must be tolerant to unaligned pointers
496 pci_set_quad(uint8_t *config
, uint64_t val
)
498 stq_le_p(config
, val
);
501 static inline uint64_t
502 pci_get_quad(const uint8_t *config
)
504 return ldq_le_p(config
);
508 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
510 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
514 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
516 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
520 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
522 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
526 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
528 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
532 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
534 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
538 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
540 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
544 * helper functions to do bit mask operation on configuration space.
545 * Just to set bit, use test-and-set and discard returned value.
546 * Just to clear bit, use test-and-clear and discard returned value.
547 * NOTE: They aren't atomic.
549 static inline uint8_t
550 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
552 uint8_t val
= pci_get_byte(config
);
553 pci_set_byte(config
, val
& ~mask
);
557 static inline uint8_t
558 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
560 uint8_t val
= pci_get_byte(config
);
561 pci_set_byte(config
, val
| mask
);
565 static inline uint16_t
566 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
568 uint16_t val
= pci_get_word(config
);
569 pci_set_word(config
, val
& ~mask
);
573 static inline uint16_t
574 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
576 uint16_t val
= pci_get_word(config
);
577 pci_set_word(config
, val
| mask
);
581 static inline uint32_t
582 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
584 uint32_t val
= pci_get_long(config
);
585 pci_set_long(config
, val
& ~mask
);
589 static inline uint32_t
590 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
592 uint32_t val
= pci_get_long(config
);
593 pci_set_long(config
, val
| mask
);
597 static inline uint64_t
598 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
600 uint64_t val
= pci_get_quad(config
);
601 pci_set_quad(config
, val
& ~mask
);
605 static inline uint64_t
606 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
608 uint64_t val
= pci_get_quad(config
);
609 pci_set_quad(config
, val
| mask
);
613 /* Access a register specified by a mask */
615 pci_set_byte_by_mask(uint8_t *config
, uint8_t mask
, uint8_t reg
)
617 uint8_t val
= pci_get_byte(config
);
618 uint8_t rval
= reg
<< ctz32(mask
);
619 pci_set_byte(config
, (~mask
& val
) | (mask
& rval
));
622 static inline uint8_t
623 pci_get_byte_by_mask(uint8_t *config
, uint8_t mask
)
625 uint8_t val
= pci_get_byte(config
);
626 return (val
& mask
) >> ctz32(mask
);
630 pci_set_word_by_mask(uint8_t *config
, uint16_t mask
, uint16_t reg
)
632 uint16_t val
= pci_get_word(config
);
633 uint16_t rval
= reg
<< ctz32(mask
);
634 pci_set_word(config
, (~mask
& val
) | (mask
& rval
));
637 static inline uint16_t
638 pci_get_word_by_mask(uint8_t *config
, uint16_t mask
)
640 uint16_t val
= pci_get_word(config
);
641 return (val
& mask
) >> ctz32(mask
);
645 pci_set_long_by_mask(uint8_t *config
, uint32_t mask
, uint32_t reg
)
647 uint32_t val
= pci_get_long(config
);
648 uint32_t rval
= reg
<< ctz32(mask
);
649 pci_set_long(config
, (~mask
& val
) | (mask
& rval
));
652 static inline uint32_t
653 pci_get_long_by_mask(uint8_t *config
, uint32_t mask
)
655 uint32_t val
= pci_get_long(config
);
656 return (val
& mask
) >> ctz32(mask
);
660 pci_set_quad_by_mask(uint8_t *config
, uint64_t mask
, uint64_t reg
)
662 uint64_t val
= pci_get_quad(config
);
663 uint64_t rval
= reg
<< ctz32(mask
);
664 pci_set_quad(config
, (~mask
& val
) | (mask
& rval
));
667 static inline uint64_t
668 pci_get_quad_by_mask(uint8_t *config
, uint64_t mask
)
670 uint64_t val
= pci_get_quad(config
);
671 return (val
& mask
) >> ctz32(mask
);
674 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
676 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
679 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
680 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
682 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
);
683 void pci_set_irq(PCIDevice
*pci_dev
, int level
);
685 static inline void pci_irq_assert(PCIDevice
*pci_dev
)
687 pci_set_irq(pci_dev
, 1);
690 static inline void pci_irq_deassert(PCIDevice
*pci_dev
)
692 pci_set_irq(pci_dev
, 0);
696 * FIXME: PCI does not work this way.
697 * All the callers to this method should be fixed.
699 static inline void pci_irq_pulse(PCIDevice
*pci_dev
)
701 pci_irq_assert(pci_dev
);
702 pci_irq_deassert(pci_dev
);
705 static inline int pci_is_express(const PCIDevice
*d
)
707 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
710 static inline uint32_t pci_config_size(const PCIDevice
*d
)
712 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;
715 static inline uint16_t pci_get_bdf(PCIDevice
*dev
)
717 return PCI_BUILD_BDF(pci_bus_num(dev
->bus
), dev
->devfn
);
720 uint16_t pci_requester_id(PCIDevice
*dev
);
722 /* DMA access functions */
723 static inline AddressSpace
*pci_get_address_space(PCIDevice
*dev
)
725 return &dev
->bus_master_as
;
728 static inline int pci_dma_rw(PCIDevice
*dev
, dma_addr_t addr
,
729 void *buf
, dma_addr_t len
, DMADirection dir
)
731 dma_memory_rw(pci_get_address_space(dev
), addr
, buf
, len
, dir
);
735 static inline int pci_dma_read(PCIDevice
*dev
, dma_addr_t addr
,
736 void *buf
, dma_addr_t len
)
738 return pci_dma_rw(dev
, addr
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
741 static inline int pci_dma_write(PCIDevice
*dev
, dma_addr_t addr
,
742 const void *buf
, dma_addr_t len
)
744 return pci_dma_rw(dev
, addr
, (void *) buf
, len
, DMA_DIRECTION_FROM_DEVICE
);
747 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
748 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
751 return ld##_l##_dma(pci_get_address_space(dev), addr); \
753 static inline void st##_s##_pci_dma(PCIDevice *dev, \
754 dma_addr_t addr, uint##_bits##_t val) \
756 st##_s##_dma(pci_get_address_space(dev), addr, val); \
759 PCI_DMA_DEFINE_LDST(ub
, b
, 8);
760 PCI_DMA_DEFINE_LDST(uw_le
, w_le
, 16)
761 PCI_DMA_DEFINE_LDST(l_le
, l_le
, 32);
762 PCI_DMA_DEFINE_LDST(q_le
, q_le
, 64);
763 PCI_DMA_DEFINE_LDST(uw_be
, w_be
, 16)
764 PCI_DMA_DEFINE_LDST(l_be
, l_be
, 32);
765 PCI_DMA_DEFINE_LDST(q_be
, q_be
, 64);
767 #undef PCI_DMA_DEFINE_LDST
769 static inline void *pci_dma_map(PCIDevice
*dev
, dma_addr_t addr
,
770 dma_addr_t
*plen
, DMADirection dir
)
774 buf
= dma_memory_map(pci_get_address_space(dev
), addr
, plen
, dir
);
778 static inline void pci_dma_unmap(PCIDevice
*dev
, void *buffer
, dma_addr_t len
,
779 DMADirection dir
, dma_addr_t access_len
)
781 dma_memory_unmap(pci_get_address_space(dev
), buffer
, len
, dir
, access_len
);
784 static inline void pci_dma_sglist_init(QEMUSGList
*qsg
, PCIDevice
*dev
,
787 qemu_sglist_init(qsg
, DEVICE(dev
), alloc_hint
, pci_get_address_space(dev
));
790 extern const VMStateDescription vmstate_pci_device
;
792 #define VMSTATE_PCI_DEVICE(_field, _state) { \
793 .name = (stringify(_field)), \
794 .size = sizeof(PCIDevice), \
795 .vmsd = &vmstate_pci_device, \
796 .flags = VMS_STRUCT, \
797 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
800 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
801 .name = (stringify(_field)), \
802 .size = sizeof(PCIDevice), \
803 .vmsd = &vmstate_pci_device, \
804 .flags = VMS_STRUCT|VMS_POINTER, \
805 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \