include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "exec/memory.h"
   5 #include "sysemu/dma.h"
   6
   7 /* PCI includes legacy ISA access.  */
   8 #include "hw/isa/isa.h"
   9
  10 extern bool pci_available;
  11
  12 /* PCI bus */
  13
  14 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  15 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
  16 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  17 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  18 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
  19 #define PCI_BDF_TO_DEVFN(x)     ((x) & 0xff)
  20 #define PCI_BUS_MAX             256
  21 #define PCI_DEVFN_MAX           256
  22 #define PCI_SLOT_MAX            32
  23 #define PCI_FUNC_MAX            8
  24
  25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  26 #include "hw/pci/pci_ids.h"
  27
  28 /* QEMU-specific Vendor and Device ID definitions */
  29
  30 /* IBM (0x1014) */
  31 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  32 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  33
  34 /* Hitachi (0x1054) */
  35 #define PCI_VENDOR_ID_HITACHI            0x1054
  36 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  37
  38 /* Apple (0x106b) */
  39 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  43 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  44
  45 /* Realtek (0x10ec) */
  46 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  47
  48 /* Xilinx (0x10ee) */
  49 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  50
  51 /* Marvell (0x11ab) */
  52 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  53
  54 /* QEMU/Bochs VGA (0x1234) */
  55 #define PCI_VENDOR_ID_QEMU               0x1234
  56 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  57 #define PCI_DEVICE_ID_QEMU_IPMI          0x1112
  58
  59 /* VMWare (0x15ad) */
  60 #define PCI_VENDOR_ID_VMWARE             0x15ad
  61 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  62 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  63 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  64 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  65 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  66 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  67 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  68
  69 /* Intel (0x8086) */
  70 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  71 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  72 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  73
  74 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  75 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  76 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  77 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  78
  79 /* legacy virtio-pci devices */
  80 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  81 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  82 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  84 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  85 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  86 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  87 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
  88
  89 /*
  90  * modern virtio-pci devices get their id assigned automatically,
  91  * there is no need to add #defines here.  It gets calculated as
  92  *
  93  * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE +
  94  *                 virtio_bus_get_vdev_id(bus)
  95  */
  96 #define PCI_DEVICE_ID_VIRTIO_10_BASE     0x1040
  97
  98 #define PCI_VENDOR_ID_REDHAT             0x1b36
  99 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
 100 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
 101 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
 102 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
 103 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
 104 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
 105 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
 106 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
 107 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
 108 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
 109 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
 110 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
 111 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
 112 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 113 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
 114 #define PCI_DEVICE_ID_REDHAT_NVME        0x0010
 115 #define PCI_DEVICE_ID_REDHAT_PVPANIC     0x0011
 116 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST   0x0012
 117 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 118
 119 #define FMT_PCIBUS                      PRIx64
 120
 121 typedef uint64_t pcibus_t;
 122
 123 struct PCIHostDeviceAddress {
 124     unsigned int domain;
 125     unsigned int bus;
 126     unsigned int slot;
 127     unsigned int function;
 128 };
 129
 130 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 131                                 uint32_t address, uint32_t data, int len);
 132 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 133                                    uint32_t address, int len);
 134 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 135                                 pcibus_t addr, pcibus_t size, int type);
 136 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 137
 138 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg);
 139 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector);
 140 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector);
 141
 142 typedef struct PCIIORegion {
 143     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 144 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 145     pcibus_t size;
 146     uint8_t type;
 147     MemoryRegion *memory;
 148     MemoryRegion *address_space;
 149 } PCIIORegion;
 150
 151 #define PCI_ROM_SLOT 6
 152 #define PCI_NUM_REGIONS 7
 153
 154 enum {
 155     QEMU_PCI_VGA_MEM,
 156     QEMU_PCI_VGA_IO_LO,
 157     QEMU_PCI_VGA_IO_HI,
 158     QEMU_PCI_VGA_NUM_REGIONS,
 159 };
 160
 161 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 162 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 163 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 164 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 165 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 166 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 167
 168 #include "hw/pci/pci_regs.h"
 169
 170 /* PCI HEADER_TYPE */
 171 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 172
 173 /* Size of the standard PCI config header */
 174 #define PCI_CONFIG_HEADER_SIZE 0x40
 175 /* Size of the standard PCI config space */
 176 #define PCI_CONFIG_SPACE_SIZE 0x100
 177 /* Size of the standard PCIe config space: 4KB */
 178 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 179
 180 #define PCI_NUM_PINS 4 /* A-D */
 181
 182 /* Bits in cap_present field. */
 183 enum {
 184     QEMU_PCI_CAP_MSI = 0x1,
 185     QEMU_PCI_CAP_MSIX = 0x2,
 186     QEMU_PCI_CAP_EXPRESS = 0x4,
 187
 188     /* multifunction capable device */
 189 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 190     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 191
 192     /* command register SERR bit enabled - unused since QEMU v5.0 */
 193 #define QEMU_PCI_CAP_SERR_BITNR 4
 194     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 195     /* Standard hot plug controller. */
 196 #define QEMU_PCI_SHPC_BITNR 5
 197     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 198 #define QEMU_PCI_SLOTID_BITNR 6
 199     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 200     /* PCI Express capability - Power Controller Present */
 201 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 202     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 203     /* Link active status in endpoint capability is always set */
 204 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
 205     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
 206 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
 207     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
 208 #define QEMU_PCIE_CXL_BITNR 10
 209     QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
 210 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11
 211     QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR),
 212 };
 213
 214 typedef struct PCIINTxRoute {
 215     enum {
 216         PCI_INTX_ENABLED,
 217         PCI_INTX_INVERTED,
 218         PCI_INTX_DISABLED,
 219     } mode;
 220     int irq;
 221 } PCIINTxRoute;
 222
 223 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 224 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 225                                       MSIMessage msg);
 226 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 227 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 228                                       unsigned int vector_start,
 229                                       unsigned int vector_end);
 230
 231 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 232                       uint8_t attr, MemoryRegion *memory);
 233 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 234                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 235 void pci_unregister_vga(PCIDevice *pci_dev);
 236 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 237
 238 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 239                        uint8_t offset, uint8_t size,
 240                        Error **errp);
 241
 242 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 243
 244 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 245
 246
 247 uint32_t pci_default_read_config(PCIDevice *d,
 248                                  uint32_t address, int len);
 249 void pci_default_write_config(PCIDevice *d,
 250                               uint32_t address, uint32_t val, int len);
 251 void pci_device_save(PCIDevice *s, QEMUFile *f);
 252 int pci_device_load(PCIDevice *s, QEMUFile *f);
 253 MemoryRegion *pci_address_space(PCIDevice *dev);
 254 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 255
 256 /*
 257  * Should not normally be used by devices. For use by sPAPR target
 258  * where QEMU emulates firmware.
 259  */
 260 int pci_bar(PCIDevice *d, int reg);
 261
 262 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 263 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 264 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 265
 266 #define TYPE_PCI_BUS "PCI"
 267 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
 268 #define TYPE_PCIE_BUS "PCIE"
 269 #define TYPE_CXL_BUS "CXL"
 270
 271 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
 272 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
 273 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
 274
 275 bool pci_bus_is_express(const PCIBus *bus);
 276
 277 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
 278                        const char *name,
 279                        MemoryRegion *address_space_mem,
 280                        MemoryRegion *address_space_io,
 281                        uint8_t devfn_min, const char *typename);
 282 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
 283                          MemoryRegion *address_space_mem,
 284                          MemoryRegion *address_space_io,
 285                          uint8_t devfn_min, const char *typename);
 286 void pci_root_bus_cleanup(PCIBus *bus);
 287 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
 288                   void *irq_opaque, int nirq);
 289 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
 290 void pci_bus_irqs_cleanup(PCIBus *bus);
 291 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 292 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus);
 293 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask);
 294 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask);
 295 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 296 static inline int pci_swizzle(int slot, int pin)
 297 {
 298     return (slot + pin) % PCI_NUM_PINS;
 299 }
 300 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 301 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
 302                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 303                               void *irq_opaque,
 304                               MemoryRegion *address_space_mem,
 305                               MemoryRegion *address_space_io,
 306                               uint8_t devfn_min, int nirq,
 307                               const char *typename);
 308 void pci_unregister_root_bus(PCIBus *bus);
 309 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 310 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 311 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 312 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 313 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 314                                           PCIINTxRoutingNotifier notifier);
 315 void pci_device_reset(PCIDevice *dev);
 316
 317 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 318                                const char *default_model,
 319                                const char *default_devaddr);
 320
 321 PCIDevice *pci_vga_init(PCIBus *bus);
 322
 323 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
 324 {
 325     return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
 326 }
 327 int pci_bus_num(PCIBus *s);
 328 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
 329 static inline int pci_dev_bus_num(const PCIDevice *dev)
 330 {
 331     return pci_bus_num(pci_get_bus(dev));
 332 }
 333
 334 int pci_bus_numa_node(PCIBus *bus);
 335 void pci_for_each_device(PCIBus *bus, int bus_num,
 336                          pci_bus_dev_fn fn,
 337                          void *opaque);
 338 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
 339                                  pci_bus_dev_fn fn,
 340                                  void *opaque);
 341 void pci_for_each_device_under_bus(PCIBus *bus,
 342                                    pci_bus_dev_fn fn, void *opaque);
 343 void pci_for_each_device_under_bus_reverse(PCIBus *bus,
 344                                            pci_bus_dev_fn fn,
 345                                            void *opaque);
 346 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
 347                                   pci_bus_fn end, void *parent_state);
 348 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 349
 350 /* Use this wrapper when specific scan order is not required. */
 351 static inline
 352 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
 353 {
 354     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 355 }
 356
 357 PCIBus *pci_device_root_bus(const PCIDevice *d);
 358 const char *pci_root_bus_path(PCIDevice *dev);
 359 bool pci_bus_bypass_iommu(PCIBus *bus);
 360 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 361 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 362 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 363
 364 void pci_device_deassert_intx(PCIDevice *dev);
 365
 366 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 367
 368 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 369 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 370
 371 pcibus_t pci_bar_address(PCIDevice *d,
 372                          int reg, uint8_t type, pcibus_t size);
 373
 374 static inline void
 375 pci_set_byte(uint8_t *config, uint8_t val)
 376 {
 377     *config = val;
 378 }
 379
 380 static inline uint8_t
 381 pci_get_byte(const uint8_t *config)
 382 {
 383     return *config;
 384 }
 385
 386 static inline void
 387 pci_set_word(uint8_t *config, uint16_t val)
 388 {
 389     stw_le_p(config, val);
 390 }
 391
 392 static inline uint16_t
 393 pci_get_word(const uint8_t *config)
 394 {
 395     return lduw_le_p(config);
 396 }
 397
 398 static inline void
 399 pci_set_long(uint8_t *config, uint32_t val)
 400 {
 401     stl_le_p(config, val);
 402 }
 403
 404 static inline uint32_t
 405 pci_get_long(const uint8_t *config)
 406 {
 407     return ldl_le_p(config);
 408 }
 409
 410 /*
 411  * PCI capabilities and/or their fields
 412  * are generally DWORD aligned only so
 413  * mechanism used by pci_set/get_quad()
 414  * must be tolerant to unaligned pointers
 415  *
 416  */
 417 static inline void
 418 pci_set_quad(uint8_t *config, uint64_t val)
 419 {
 420     stq_le_p(config, val);
 421 }
 422
 423 static inline uint64_t
 424 pci_get_quad(const uint8_t *config)
 425 {
 426     return ldq_le_p(config);
 427 }
 428
 429 static inline void
 430 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 431 {
 432     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 433 }
 434
 435 static inline void
 436 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 437 {
 438     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 439 }
 440
 441 static inline void
 442 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 443 {
 444     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 445 }
 446
 447 static inline void
 448 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 449 {
 450     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 451 }
 452
 453 static inline void
 454 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 455 {
 456     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 457 }
 458
 459 static inline void
 460 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 461 {
 462     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 463 }
 464
 465 /*
 466  * helper functions to do bit mask operation on configuration space.
 467  * Just to set bit, use test-and-set and discard returned value.
 468  * Just to clear bit, use test-and-clear and discard returned value.
 469  * NOTE: They aren't atomic.
 470  */
 471 static inline uint8_t
 472 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 473 {
 474     uint8_t val = pci_get_byte(config);
 475     pci_set_byte(config, val & ~mask);
 476     return val & mask;
 477 }
 478
 479 static inline uint8_t
 480 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 481 {
 482     uint8_t val = pci_get_byte(config);
 483     pci_set_byte(config, val | mask);
 484     return val & mask;
 485 }
 486
 487 static inline uint16_t
 488 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 489 {
 490     uint16_t val = pci_get_word(config);
 491     pci_set_word(config, val & ~mask);
 492     return val & mask;
 493 }
 494
 495 static inline uint16_t
 496 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 497 {
 498     uint16_t val = pci_get_word(config);
 499     pci_set_word(config, val | mask);
 500     return val & mask;
 501 }
 502
 503 static inline uint32_t
 504 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 505 {
 506     uint32_t val = pci_get_long(config);
 507     pci_set_long(config, val & ~mask);
 508     return val & mask;
 509 }
 510
 511 static inline uint32_t
 512 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 513 {
 514     uint32_t val = pci_get_long(config);
 515     pci_set_long(config, val | mask);
 516     return val & mask;
 517 }
 518
 519 static inline uint64_t
 520 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 521 {
 522     uint64_t val = pci_get_quad(config);
 523     pci_set_quad(config, val & ~mask);
 524     return val & mask;
 525 }
 526
 527 static inline uint64_t
 528 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 529 {
 530     uint64_t val = pci_get_quad(config);
 531     pci_set_quad(config, val | mask);
 532     return val & mask;
 533 }
 534
 535 /* Access a register specified by a mask */
 536 static inline void
 537 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 538 {
 539     uint8_t val = pci_get_byte(config);
 540     uint8_t rval;
 541
 542     assert(mask);
 543     rval = reg << ctz32(mask);
 544     pci_set_byte(config, (~mask & val) | (mask & rval));
 545 }
 546
 547 static inline void
 548 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 549 {
 550     uint16_t val = pci_get_word(config);
 551     uint16_t rval;
 552
 553     assert(mask);
 554     rval = reg << ctz32(mask);
 555     pci_set_word(config, (~mask & val) | (mask & rval));
 556 }
 557
 558 static inline void
 559 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 560 {
 561     uint32_t val = pci_get_long(config);
 562     uint32_t rval;
 563
 564     assert(mask);
 565     rval = reg << ctz32(mask);
 566     pci_set_long(config, (~mask & val) | (mask & rval));
 567 }
 568
 569 static inline void
 570 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 571 {
 572     uint64_t val = pci_get_quad(config);
 573     uint64_t rval;
 574
 575     assert(mask);
 576     rval = reg << ctz32(mask);
 577     pci_set_quad(config, (~mask & val) | (mask & rval));
 578 }
 579
 580 PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
 581                                     const char *name);
 582 PCIDevice *pci_new(int devfn, const char *name);
 583 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
 584
 585 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 586                                            bool multifunction,
 587                                            const char *name);
 588 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 589
 590 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
 591
 592 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 593 void pci_set_irq(PCIDevice *pci_dev, int level);
 594
 595 static inline void pci_irq_assert(PCIDevice *pci_dev)
 596 {
 597     pci_set_irq(pci_dev, 1);
 598 }
 599
 600 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 601 {
 602     pci_set_irq(pci_dev, 0);
 603 }
 604
 605 /*
 606  * FIXME: PCI does not work this way.
 607  * All the callers to this method should be fixed.
 608  */
 609 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 610 {
 611     pci_irq_assert(pci_dev);
 612     pci_irq_deassert(pci_dev);
 613 }
 614
 615 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
 616 void pci_set_power(PCIDevice *pci_dev, bool state);
 617
 618 #endif