]>
git.proxmox.com Git - mirror_qemu.git/blob - include/hw/pci-host/apb.h
4 #include "qemu-common.h"
5 #include "hw/pci/pci_host.h"
9 #define IOMMU_PAGE_SIZE_8K (1ULL << 13)
10 #define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
11 #define IOMMU_PAGE_SIZE_64K (1ULL << 16)
12 #define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
14 #define IOMMU_CTRL 0x0
15 #define IOMMU_CTRL_TBW_SIZE (1ULL << 2)
16 #define IOMMU_CTRL_MMU_EN (1ULL)
18 #define IOMMU_CTRL_TSB_SHIFT 16
20 #define IOMMU_BASE 0x8
21 #define IOMMU_FLUSH 0x10
23 #define IOMMU_TTE_DATA_V (1ULL << 63)
24 #define IOMMU_TTE_DATA_SIZE (1ULL << 61)
25 #define IOMMU_TTE_DATA_W (1ULL << 1)
27 #define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
28 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
30 #define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
31 #define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
32 #define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
33 #define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
34 #define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
35 #define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL
36 #define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL
37 #define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL
39 #define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL
40 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
41 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
42 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
43 #define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL
44 #define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL
46 typedef struct IOMMUState
{
47 AddressSpace iommu_as
;
48 IOMMUMemoryRegion iommu
;
50 uint64_t regs
[IOMMU_NREGS
];
53 #define TYPE_APB "pbm"
55 #define APB_DEVICE(obj) \
56 OBJECT_CHECK(APBState, (obj), TYPE_APB)
58 #define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region"
60 typedef struct APBState
{
61 PCIHostState parent_obj
;
63 MemoryRegion apb_config
;
64 MemoryRegion pci_config
;
65 MemoryRegion pci_mmio
;
66 MemoryRegion pci_ioport
;
69 uint32_t pci_control
[16];
70 uint32_t pci_irq_map
[8];
71 uint32_t pci_err_irq_map
[4];
72 uint32_t obio_irq_map
[32];
75 unsigned int irq_request
;
76 uint32_t reset_control
;
77 unsigned int nr_resets
;
80 typedef struct PBMPCIBridge
{
84 /* Is this busA with in-built devices (ebus)? */
88 #define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
89 #define PBM_PCI_BRIDGE(obj) \
90 OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
92 PCIBus
*pci_apb_init(hwaddr special_base
,
94 qemu_irq
*ivec_irqs
, PCIBus
**bus2
, PCIBus
**bus3
);