2 * QEMU PowerPC PowerNV (POWER9) PHB4 model
4 * Copyright (c) 2018-2020, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #ifndef PCI_HOST_PNV_PHB4_H
11 #define PCI_HOST_PNV_PHB4_H
13 #include "hw/pci-host/pnv_phb.h"
14 #include "hw/pci/pci_bus.h"
15 #include "hw/ppc/pnv.h"
16 #include "hw/ppc/xive.h"
17 #include "qom/object.h"
19 typedef struct PnvPhb4PecState PnvPhb4PecState
;
20 typedef struct PnvPhb4PecStack PnvPhb4PecStack
;
21 typedef struct PnvPHB4 PnvPHB4
;
22 typedef struct PnvChip PnvChip
;
25 * We have one such address space wrapper per possible device under
26 * the PHB since they need to be assigned statically at qemu device
27 * creation time. The relationship to a PE is done later
28 * dynamically. This means we can potentially create a lot of these
29 * guys. Q35 stores them as some kind of radix tree but we never
30 * really need to do fast lookups so instead we simply keep a QLIST of
31 * them for now, we can add the radix if needed later on.
33 * We do cache the PE number to speed things up a bit though.
35 typedef struct PnvPhb4DMASpace
{
38 int pe_num
; /* Cached PE number */
39 #define PHB_INVALID_PE (-1)
42 IOMMUMemoryRegion dma_mr
;
43 MemoryRegion msi32_mr
;
44 MemoryRegion msi64_mr
;
45 QLIST_ENTRY(PnvPhb4DMASpace
) list
;
51 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
52 struct PnvPHB4RootBus
{
58 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus
, PNV_PHB4_ROOT_BUS
)
61 * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
63 #define TYPE_PNV_PHB4 "pnv-phb4"
64 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4
, PNV_PHB4
)
66 #define PNV_PHB4_MAX_LSIs 8
67 #define PNV_PHB4_MAX_INTs 4096
68 #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2)
69 #define PNV_PHB4_MAX_MMIO_WINDOWS 32
70 #define PNV_PHB4_MIN_MMIO_WINDOWS 16
71 #define PNV_PHB4_NUM_REGS (0x3000 >> 3)
72 #define PNV_PHB4_MAX_PEs 512
73 #define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2)
74 #define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64)
75 #define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2)
77 #define PNV_PHB4_VERSION 0x000000a400000002ull
78 #define PNV_PHB4_DEVICE_ID 0x04c1
80 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
95 /* Main register images */
96 uint64_t regs
[PNV_PHB4_NUM_REGS
];
99 /* Extra SCOM-only register */
100 uint64_t scom_hv_ind_addr_reg
;
103 * Geometry of the PHB. There are two types, small and big PHBs, a
104 * number of resources (number of PEs, windows etc...) are doubled
109 /* Memory regions for MMIO space */
110 MemoryRegion mr_mmio
[PNV_PHB4_MAX_MMIO_WINDOWS
];
113 MemoryRegion pci_mmio
;
116 /* PCI registers (excluding pass-through) */
117 #define PHB4_PEC_PCI_STK_REGS_COUNT 0xf
118 uint64_t pci_regs
[PHB4_PEC_PCI_STK_REGS_COUNT
];
119 MemoryRegion pci_regs_mr
;
122 #define PHB4_PEC_NEST_STK_REGS_COUNT 0x17
123 uint64_t nest_regs
[PHB4_PEC_NEST_STK_REGS_COUNT
];
124 MemoryRegion nest_regs_mr
;
126 /* PHB pass-through XSCOM */
127 MemoryRegion phb_regs_mr
;
129 /* Memory windows from PowerBus to PHB */
139 /* On-chip IODA tables */
140 uint64_t ioda_LIST
[PNV_PHB4_MAX_LSIs
];
141 uint64_t ioda_MIST
[PNV_PHB4_MAX_MIST
];
142 uint64_t ioda_TVT
[PNV_PHB4_MAX_TVEs
];
143 uint64_t ioda_MBT
[PNV_PHB4_MAX_MBEs
];
144 uint64_t ioda_MDT
[PNV_PHB4_MAX_PEs
];
145 uint64_t ioda_PEEV
[PNV_PHB4_MAX_PEEVs
];
148 * The internal PESTA/B is 2 bits per PE split into two tables, we
149 * store them in a single array here to avoid wasting space.
151 uint8_t ioda_PEST_AB
[PNV_PHB4_MAX_PEs
];
153 /* P9 Interrupt generation */
157 QLIST_HEAD(, PnvPhb4DMASpace
) dma_spaces
;
160 void pnv_phb4_pic_print_info(PnvPHB4
*phb
, Monitor
*mon
);
161 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState
*pec
, int stack_index
);
162 void pnv_phb4_bus_init(DeviceState
*dev
, PnvPHB4
*phb
);
163 extern const MemoryRegionOps pnv_phb4_xscom_ops
;
166 * PHB4 PEC (PCI Express Controller)
168 #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec"
169 OBJECT_DECLARE_TYPE(PnvPhb4PecState
, PnvPhb4PecClass
, PNV_PHB4_PEC
)
171 struct PnvPhb4PecState
{
174 /* PEC number in chip */
178 MemoryRegion
*system_memory
;
180 /* Nest registers, excuding per-stack */
181 #define PHB4_PEC_NEST_REGS_COUNT 0xf
182 uint64_t nest_regs
[PHB4_PEC_NEST_REGS_COUNT
];
183 MemoryRegion nest_regs_mr
;
185 /* PCI registers, excluding per-stack */
186 #define PHB4_PEC_PCI_REGS_COUNT 0x3
187 uint64_t pci_regs
[PHB4_PEC_PCI_REGS_COUNT
];
188 MemoryRegion pci_regs_mr
;
197 struct PnvPhb4PecClass
{
198 DeviceClass parent_class
;
200 uint32_t (*xscom_nest_base
)(PnvPhb4PecState
*pec
);
201 uint32_t xscom_nest_size
;
202 uint32_t (*xscom_pci_base
)(PnvPhb4PecState
*pec
);
203 uint32_t xscom_pci_size
;
206 const char *stk_compat
;
209 const char *phb_type
;
210 const uint32_t *num_phbs
;
214 * POWER10 definitions
217 #define TYPE_PNV_PHB5 "pnv-phb5"
218 #define PNV_PHB5(obj) \
219 OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5)
221 #define PNV_PHB5_VERSION 0x000000a500000001ull
222 #define PNV_PHB5_DEVICE_ID 0x0652
224 #define TYPE_PNV_PHB5_PEC "pnv-phb5-pec"
225 #define PNV_PHB5_PEC(obj) \
226 OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC)
228 #endif /* PCI_HOST_PNV_PHB4_H */