include/hw/pci-host/pnv_phb4.h

   1 /*
   2  * QEMU PowerPC PowerNV (POWER9) PHB4 model
   3  *
   4  * Copyright (c) 2018-2020, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef PCI_HOST_PNV_PHB4_H
  11 #define PCI_HOST_PNV_PHB4_H
  12
  13 #include "hw/pci/pcie_host.h"
  14 #include "hw/pci/pcie_port.h"
  15 #include "hw/ppc/xive.h"
  16 #include "qom/object.h"
  17
  18 typedef struct PnvPhb4PecState PnvPhb4PecState;
  19 typedef struct PnvPhb4PecStack PnvPhb4PecStack;
  20 typedef struct PnvPHB4 PnvPHB4;
  21 typedef struct PnvChip PnvChip;
  22
  23 /*
  24  * We have one such address space wrapper per possible device under
  25  * the PHB since they need to be assigned statically at qemu device
  26  * creation time. The relationship to a PE is done later
  27  * dynamically. This means we can potentially create a lot of these
  28  * guys. Q35 stores them as some kind of radix tree but we never
  29  * really need to do fast lookups so instead we simply keep a QLIST of
  30  * them for now, we can add the radix if needed later on.
  31  *
  32  * We do cache the PE number to speed things up a bit though.
  33  */
  34 typedef struct PnvPhb4DMASpace {
  35     PCIBus *bus;
  36     uint8_t devfn;
  37     int pe_num;         /* Cached PE number */
  38 #define PHB_INVALID_PE (-1)
  39     PnvPHB4 *phb;
  40     AddressSpace dma_as;
  41     IOMMUMemoryRegion dma_mr;
  42     MemoryRegion msi32_mr;
  43     MemoryRegion msi64_mr;
  44     QLIST_ENTRY(PnvPhb4DMASpace) list;
  45 } PnvPhb4DMASpace;
  46
  47 /*
  48  * PHB4 PCIe Root port
  49  */
  50 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
  51 #define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
  52
  53 typedef struct PnvPHB4RootPort {
  54     PCIESlot parent_obj;
  55 } PnvPHB4RootPort;
  56
  57 /*
  58  * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
  59  */
  60 #define TYPE_PNV_PHB4 "pnv-phb4"
  61 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
  62
  63 #define PNV_PHB4_MAX_LSIs          8
  64 #define PNV_PHB4_MAX_INTs          4096
  65 #define PNV_PHB4_MAX_MIST          (PNV_PHB4_MAX_INTs >> 2)
  66 #define PNV_PHB4_MAX_MMIO_WINDOWS  32
  67 #define PNV_PHB4_MIN_MMIO_WINDOWS  16
  68 #define PNV_PHB4_NUM_REGS          (0x3000 >> 3)
  69 #define PNV_PHB4_MAX_PEs           512
  70 #define PNV_PHB4_MAX_TVEs          (PNV_PHB4_MAX_PEs * 2)
  71 #define PNV_PHB4_MAX_PEEVs         (PNV_PHB4_MAX_PEs / 64)
  72 #define PNV_PHB4_MAX_MBEs          (PNV_PHB4_MAX_MMIO_WINDOWS * 2)
  73
  74 #define PNV_PHB4_VERSION           0x000000a400000002ull
  75 #define PNV_PHB4_DEVICE_ID         0x04c1
  76
  77 #define PCI_MMIO_TOTAL_SIZE        (0x1ull << 60)
  78
  79 struct PnvPHB4 {
  80     PCIExpressHost parent_obj;
  81
  82     uint32_t chip_id;
  83     uint32_t phb_id;
  84
  85     uint64_t version;
  86
  87     /* The owner PEC */
  88     PnvPhb4PecState *pec;
  89
  90     char bus_path[8];
  91
  92     /* Main register images */
  93     uint64_t regs[PNV_PHB4_NUM_REGS];
  94     MemoryRegion mr_regs;
  95
  96     /* Extra SCOM-only register */
  97     uint64_t scom_hv_ind_addr_reg;
  98
  99     /*
 100      * Geometry of the PHB. There are two types, small and big PHBs, a
 101      * number of resources (number of PEs, windows etc...) are doubled
 102      * for a big PHB
 103      */
 104     bool big_phb;
 105
 106     /* Memory regions for MMIO space */
 107     MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS];
 108
 109     /* PCI side space */
 110     MemoryRegion pci_mmio;
 111     MemoryRegion pci_io;
 112
 113     /* PCI registers (excluding pass-through) */
 114 #define PHB4_PEC_PCI_STK_REGS_COUNT  0xf
 115     uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT];
 116     MemoryRegion pci_regs_mr;
 117
 118     /* Nest registers */
 119 #define PHB4_PEC_NEST_STK_REGS_COUNT  0x17
 120     uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT];
 121     MemoryRegion nest_regs_mr;
 122
 123     /* PHB pass-through XSCOM */
 124     MemoryRegion phb_regs_mr;
 125
 126     /* Memory windows from PowerBus to PHB */
 127     MemoryRegion phbbar;
 128     MemoryRegion intbar;
 129     MemoryRegion mmbar0;
 130     MemoryRegion mmbar1;
 131     uint64_t mmio0_base;
 132     uint64_t mmio0_size;
 133     uint64_t mmio1_base;
 134     uint64_t mmio1_size;
 135
 136     /* On-chip IODA tables */
 137     uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs];
 138     uint64_t ioda_MIST[PNV_PHB4_MAX_MIST];
 139     uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs];
 140     uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs];
 141     uint64_t ioda_MDT[PNV_PHB4_MAX_PEs];
 142     uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs];
 143
 144     /*
 145      * The internal PESTA/B is 2 bits per PE split into two tables, we
 146      * store them in a single array here to avoid wasting space.
 147      */
 148     uint8_t  ioda_PEST_AB[PNV_PHB4_MAX_PEs];
 149
 150     /* P9 Interrupt generation */
 151     XiveSource xsrc;
 152     qemu_irq *qirqs;
 153
 154     QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces;
 155 };
 156
 157 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
 158 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);
 159 extern const MemoryRegionOps pnv_phb4_xscom_ops;
 160
 161 /*
 162  * PHB4 PEC (PCI Express Controller)
 163  */
 164 #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec"
 165 OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC)
 166
 167 struct PnvPhb4PecState {
 168     DeviceState parent;
 169
 170     /* PEC number in chip */
 171     uint32_t index;
 172     uint32_t chip_id;
 173
 174     MemoryRegion *system_memory;
 175
 176     /* Nest registers, excuding per-stack */
 177 #define PHB4_PEC_NEST_REGS_COUNT    0xf
 178     uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT];
 179     MemoryRegion nest_regs_mr;
 180
 181     /* PCI registers, excluding per-stack */
 182 #define PHB4_PEC_PCI_REGS_COUNT     0x2
 183     uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT];
 184     MemoryRegion pci_regs_mr;
 185
 186     /* PHBs */
 187     uint32_t num_phbs;
 188
 189     PnvChip *chip;
 190 };
 191
 192
 193 struct PnvPhb4PecClass {
 194     DeviceClass parent_class;
 195
 196     uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec);
 197     uint32_t xscom_nest_size;
 198     uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec);
 199     uint32_t xscom_pci_size;
 200     const char *compat;
 201     int compat_size;
 202     const char *stk_compat;
 203     int stk_compat_size;
 204     uint64_t version;
 205     const uint32_t *num_phbs;
 206     const char *rp_model;
 207 };
 208
 209 #endif /* PCI_HOST_PNV_PHB4_H */