include/hw/pci-host/sabre.h

   1 #ifndef HW_PCI_HOST_SABRE_H
   2 #define HW_PCI_HOST_SABRE_H
   3
   4 #include "hw/pci/pci.h"
   5 #include "hw/pci/pci_host.h"
   6 #include "hw/sparc/sun4u_iommu.h"
   7 #include "qom/object.h"
   8
   9 #define MAX_IVEC 0x40
  10
  11 /* OBIO IVEC IRQs */
  12 #define OBIO_HDD_IRQ         0x20
  13 #define OBIO_NIC_IRQ         0x21
  14 #define OBIO_LPT_IRQ         0x22
  15 #define OBIO_FDD_IRQ         0x27
  16 #define OBIO_KBD_IRQ         0x29
  17 #define OBIO_MSE_IRQ         0x2a
  18 #define OBIO_SER_IRQ         0x2b
  19
  20 struct SabrePCIState {
  21     PCIDevice parent_obj;
  22 };
  23 typedef struct SabrePCIState SabrePCIState;
  24
  25 #define TYPE_SABRE_PCI_DEVICE "sabre-pci"
  26 #define SABRE_PCI_DEVICE(obj) \
  27     OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
  28
  29 struct SabreState {
  30     PCIHostState parent_obj;
  31
  32     hwaddr special_base;
  33     hwaddr mem_base;
  34     MemoryRegion sabre_config;
  35     MemoryRegion pci_config;
  36     MemoryRegion pci_mmio;
  37     MemoryRegion pci_ioport;
  38     uint64_t pci_irq_in;
  39     IOMMUState *iommu;
  40     PCIBridge *bridgeA;
  41     PCIBridge *bridgeB;
  42     uint32_t pci_control[16];
  43     uint32_t pci_irq_map[8];
  44     uint32_t pci_err_irq_map[4];
  45     uint32_t obio_irq_map[32];
  46     qemu_irq ivec_irqs[MAX_IVEC];
  47     unsigned int irq_request;
  48     uint32_t reset_control;
  49     unsigned int nr_resets;
  50 };
  51 typedef struct SabreState SabreState;
  52
  53 #define TYPE_SABRE "sabre"
  54 #define SABRE_DEVICE(obj) \
  55     OBJECT_CHECK(SabreState, (obj), TYPE_SABRE)
  56
  57 #endif