2 * QEMU SPAPR PCI BUS definitions
4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef PCI_HOST_SPAPR_H
21 #define PCI_HOST_SPAPR_H
23 #include "hw/ppc/spapr.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/pci_host.h"
26 #include "hw/ppc/xics.h"
28 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
30 #define SPAPR_PCI_HOST_BRIDGE(obj) \
31 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
33 #define SPAPR_PCI_DMA_MAX_WINDOWS 2
35 typedef struct sPAPRPHBState sPAPRPHBState
;
37 typedef struct spapr_pci_msi
{
42 typedef struct spapr_pci_msi_mig
{
47 struct sPAPRPHBState
{
48 PCIHostState parent_obj
;
55 MemoryRegion memspace
, iospace
;
56 hwaddr mem_win_addr
, mem_win_size
, mem64_win_addr
, mem64_win_size
;
57 uint64_t mem64_win_pciaddr
;
58 hwaddr io_win_addr
, io_win_size
;
59 MemoryRegion mem32window
, mem64window
, iowindow
, msiwindow
;
61 uint32_t dma_liobn
[SPAPR_PCI_DMA_MAX_WINDOWS
];
62 hwaddr dma_win_addr
, dma_win_size
;
63 AddressSpace iommu_as
;
64 MemoryRegion iommu_root
;
66 struct spapr_pci_lsi
{
68 } lsi_table
[PCI_NUM_PINS
];
71 /* Temporary cache for migration purposes */
73 spapr_pci_msi_mig
*msi_devs
;
75 QLIST_ENTRY(sPAPRPHBState
) list
;
78 uint64_t page_size_mask
;
79 uint64_t dma64_win_addr
;
83 bool pcie_ecs
; /* Allow access to PCIe extended config space? */
85 /* Fields for migration compatibility hacks */
86 bool pre_2_8_migration
;
88 hwaddr mig_mem_win_addr
, mig_mem_win_size
;
89 hwaddr mig_io_win_addr
, mig_io_win_size
;
92 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
93 #define SPAPR_PCI_MEM32_WIN_SIZE \
94 ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
95 #define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */
97 /* All PCI outbound windows will be within this range */
98 #define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */
99 #define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */
101 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
102 SPAPR_PCI_MEM64_WIN_SIZE - 1)
104 #define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000
105 #define SPAPR_PCI_IO_WIN_SIZE 0x10000
107 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
109 static inline qemu_irq
spapr_phb_lsi_qirq(struct sPAPRPHBState
*phb
, int pin
)
111 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
113 return spapr_qirq(spapr
, phb
->lsi_table
[pin
].irq
);
116 int spapr_populate_pci_dt(sPAPRPHBState
*phb
, uint32_t xics_phandle
, void *fdt
,
119 void spapr_pci_rtas_init(void);
121 sPAPRPHBState
*spapr_pci_find_phb(sPAPRMachineState
*spapr
, uint64_t buid
);
122 PCIDevice
*spapr_pci_find_dev(sPAPRMachineState
*spapr
, uint64_t buid
,
123 uint32_t config_addr
);
125 /* PCI release callback. */
126 void spapr_phb_remove_pci_device_cb(DeviceState
*dev
);
130 bool spapr_phb_eeh_available(sPAPRPHBState
*sphb
);
131 int spapr_phb_vfio_eeh_set_option(sPAPRPHBState
*sphb
,
132 unsigned int addr
, int option
);
133 int spapr_phb_vfio_eeh_get_state(sPAPRPHBState
*sphb
, int *state
);
134 int spapr_phb_vfio_eeh_reset(sPAPRPHBState
*sphb
, int option
);
135 int spapr_phb_vfio_eeh_configure(sPAPRPHBState
*sphb
);
136 void spapr_phb_vfio_reset(DeviceState
*qdev
);
138 static inline bool spapr_phb_eeh_available(sPAPRPHBState
*sphb
)
142 static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState
*sphb
,
143 unsigned int addr
, int option
)
145 return RTAS_OUT_HW_ERROR
;
147 static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState
*sphb
,
150 return RTAS_OUT_HW_ERROR
;
152 static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState
*sphb
, int option
)
154 return RTAS_OUT_HW_ERROR
;
156 static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState
*sphb
)
158 return RTAS_OUT_HW_ERROR
;
160 static inline void spapr_phb_vfio_reset(DeviceState
*qdev
)
165 void spapr_phb_dma_reset(sPAPRPHBState
*sphb
);
167 #endif /* PCI_HOST_SPAPR_H */