include/hw/ppc/pnv.h

   1 /*
   2  * QEMU PowerPC PowerNV various definitions
   3  *
   4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_PNV_H
  21 #define PPC_PNV_H
  22
  23 #include "hw/boards.h"
  24 #include "hw/sysbus.h"
  25 #include "hw/ipmi/ipmi.h"
  26 #include "hw/ppc/pnv_lpc.h"
  27 #include "hw/ppc/pnv_psi.h"
  28 #include "hw/ppc/pnv_occ.h"
  29 #include "hw/ppc/pnv_homer.h"
  30 #include "hw/ppc/pnv_xive.h"
  31 #include "hw/ppc/pnv_core.h"
  32
  33 #define TYPE_PNV_CHIP "pnv-chip"
  34 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
  35 #define PNV_CHIP_CLASS(klass) \
  36      OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
  37 #define PNV_CHIP_GET_CLASS(obj) \
  38      OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
  39
  40 typedef enum PnvChipType {
  41     PNV_CHIP_POWER8E,     /* AKA Murano (default) */
  42     PNV_CHIP_POWER8,      /* AKA Venice */
  43     PNV_CHIP_POWER8NVL,   /* AKA Naples */
  44     PNV_CHIP_POWER9,      /* AKA Nimbus */
  45 } PnvChipType;
  46
  47 typedef struct PnvChip {
  48     /*< private >*/
  49     SysBusDevice parent_obj;
  50
  51     /*< public >*/
  52     uint32_t     chip_id;
  53     uint64_t     ram_start;
  54     uint64_t     ram_size;
  55
  56     uint32_t     nr_cores;
  57     uint64_t     cores_mask;
  58     void         *cores;
  59
  60     MemoryRegion xscom_mmio;
  61     MemoryRegion xscom;
  62     AddressSpace xscom_as;
  63
  64     gchar        *dt_isa_nodename;
  65 } PnvChip;
  66
  67 #define TYPE_PNV8_CHIP "pnv8-chip"
  68 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
  69
  70 typedef struct Pnv8Chip {
  71     /*< private >*/
  72     PnvChip      parent_obj;
  73
  74     /*< public >*/
  75     MemoryRegion icp_mmio;
  76
  77     PnvLpcController lpc;
  78     Pnv8Psi      psi;
  79     PnvOCC       occ;
  80     PnvHomer     homer;
  81 } Pnv8Chip;
  82
  83 #define TYPE_PNV9_CHIP "pnv9-chip"
  84 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
  85
  86 typedef struct Pnv9Chip {
  87     /*< private >*/
  88     PnvChip      parent_obj;
  89
  90     /*< public >*/
  91     PnvXive      xive;
  92     Pnv9Psi      psi;
  93     PnvLpcController lpc;
  94     PnvOCC       occ;
  95     PnvHomer     homer;
  96
  97     uint32_t     nr_quads;
  98     PnvQuad      *quads;
  99 } Pnv9Chip;
 100
 101 typedef struct PnvChipClass {
 102     /*< private >*/
 103     SysBusDeviceClass parent_class;
 104
 105     /*< public >*/
 106     PnvChipType  chip_type;
 107     uint64_t     chip_cfam_id;
 108     uint64_t     cores_mask;
 109
 110     DeviceRealize parent_realize;
 111
 112     uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
 113     void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
 114     ISABus *(*isa_create)(PnvChip *chip, Error **errp);
 115     void (*dt_populate)(PnvChip *chip, void *fdt);
 116     void (*pic_print_info)(PnvChip *chip, Monitor *mon);
 117 } PnvChipClass;
 118
 119 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
 120 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
 121
 122 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
 123 #define PNV_CHIP_POWER8E(obj) \
 124     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
 125
 126 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
 127 #define PNV_CHIP_POWER8(obj) \
 128     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
 129
 130 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
 131 #define PNV_CHIP_POWER8NVL(obj) \
 132     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
 133
 134 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
 135 #define PNV_CHIP_POWER9(obj) \
 136     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
 137
 138 /*
 139  * This generates a HW chip id depending on an index, as found on a
 140  * two socket system with dual chip modules :
 141  *
 142  *    0x0, 0x1, 0x10, 0x11
 143  *
 144  * 4 chips should be the maximum
 145  *
 146  * TODO: use a machine property to define the chip ids
 147  */
 148 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
 149
 150 /*
 151  * Converts back a HW chip id to an index. This is useful to calculate
 152  * the MMIO addresses of some controllers which depend on the chip id.
 153  */
 154 #define PNV_CHIP_INDEX(chip)                                    \
 155     (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
 156
 157 #define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
 158 #define PNV_MACHINE(obj) \
 159     OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
 160
 161 typedef struct PnvMachineState {
 162     /*< private >*/
 163     MachineState parent_obj;
 164
 165     uint32_t     initrd_base;
 166     long         initrd_size;
 167
 168     uint32_t     num_chips;
 169     PnvChip      **chips;
 170
 171     ISABus       *isa_bus;
 172     uint32_t     cpld_irqstate;
 173
 174     IPMIBmc      *bmc;
 175     Notifier     powerdown_notifier;
 176 } PnvMachineState;
 177
 178 static inline bool pnv_chip_is_power9(const PnvChip *chip)
 179 {
 180     return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
 181 }
 182
 183 static inline bool pnv_is_power9(PnvMachineState *pnv)
 184 {
 185     return pnv_chip_is_power9(pnv->chips[0]);
 186 }
 187
 188 #define PNV_FDT_ADDR          0x01000000
 189 #define PNV_TIMEBASE_FREQ     512000000ULL
 190
 191 /*
 192  * BMC helpers
 193  */
 194 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
 195 void pnv_bmc_powerdown(IPMIBmc *bmc);
 196
 197 /*
 198  * POWER8 MMIO base addresses
 199  */
 200 #define PNV_XSCOM_SIZE        0x800000000ull
 201 #define PNV_XSCOM_BASE(chip)                                            \
 202     (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
 203
 204 #define PNV_OCC_COMMON_AREA_SIZE    0x0000000000700000ull
 205 #define PNV_OCC_COMMON_AREA(chip)                                       \
 206     (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
 207                          PNV_OCC_COMMON_AREA_SIZE))
 208
 209 #define PNV_HOMER_SIZE              0x0000000000300000ull
 210 #define PNV_HOMER_BASE(chip)                                            \
 211     (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
 212
 213
 214 /*
 215  * XSCOM 0x20109CA defines the ICP BAR:
 216  *
 217  * 0:29   : bits 14 to 43 of address to define 1 MB region.
 218  * 30     : 1 to enable ICP to receive loads/stores against its BAR region
 219  * 31:63  : Constant 0
 220  *
 221  * Usually defined as :
 222  *
 223  *      0xffffe00200000000 -> 0x0003ffff80000000
 224  *      0xffffe00600000000 -> 0x0003ffff80100000
 225  *      0xffffe02200000000 -> 0x0003ffff80800000
 226  *      0xffffe02600000000 -> 0x0003ffff80900000
 227  */
 228 #define PNV_ICP_SIZE         0x0000000000100000ull
 229 #define PNV_ICP_BASE(chip)                                              \
 230     (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
 231
 232
 233 #define PNV_PSIHB_SIZE       0x0000000000100000ull
 234 #define PNV_PSIHB_BASE(chip) \
 235     (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
 236
 237 #define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
 238 #define PNV_PSIHB_FSP_BASE(chip) \
 239     (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
 240      PNV_PSIHB_FSP_SIZE)
 241
 242 /*
 243  * POWER9 MMIO base addresses
 244  */
 245 #define PNV9_CHIP_BASE(chip, base)   \
 246     ((base) + ((uint64_t) (chip)->chip_id << 42))
 247
 248 #define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
 249 #define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
 250
 251 #define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
 252 #define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
 253
 254 #define PNV9_LPCM_SIZE               0x0000000100000000ull
 255 #define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
 256
 257 #define PNV9_PSIHB_SIZE              0x0000000000100000ull
 258 #define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
 259
 260 #define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
 261 #define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
 262
 263 #define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
 264 #define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
 265
 266 #define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
 267 #define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
 268
 269 #define PNV9_XSCOM_SIZE              0x0000000400000000ull
 270 #define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
 271
 272 #define PNV9_OCC_COMMON_AREA_SIZE    0x0000000000700000ull
 273 #define PNV9_OCC_COMMON_AREA(chip)                                      \
 274     (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
 275                            PNV9_OCC_COMMON_AREA_SIZE))
 276
 277 #define PNV9_HOMER_SIZE              0x0000000000300000ull
 278 #define PNV9_HOMER_BASE(chip)                                           \
 279     (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
 280 #endif /* PPC_PNV_H */