2 * QEMU PowerPC PowerNV various definitions
4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "hw/boards.h"
23 #include "hw/sysbus.h"
24 #include "hw/ipmi/ipmi.h"
25 #include "hw/ppc/pnv_lpc.h"
26 #include "hw/ppc/pnv_psi.h"
27 #include "hw/ppc/pnv_occ.h"
28 #include "hw/ppc/pnv_xive.h"
30 #define TYPE_PNV_CHIP "pnv-chip"
31 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
32 #define PNV_CHIP_CLASS(klass) \
33 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
34 #define PNV_CHIP_GET_CLASS(obj) \
35 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
37 typedef enum PnvChipType
{
38 PNV_CHIP_POWER8E
, /* AKA Murano (default) */
39 PNV_CHIP_POWER8
, /* AKA Venice */
40 PNV_CHIP_POWER8NVL
, /* AKA Naples */
41 PNV_CHIP_POWER9
, /* AKA Nimbus */
44 typedef struct PnvChip
{
46 SysBusDevice parent_obj
;
58 MemoryRegion xscom_mmio
;
60 AddressSpace xscom_as
;
63 #define TYPE_PNV8_CHIP "pnv8-chip"
64 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
66 typedef struct Pnv8Chip
{
71 MemoryRegion icp_mmio
;
78 #define TYPE_PNV9_CHIP "pnv9-chip"
79 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
81 typedef struct Pnv9Chip
{
89 typedef struct PnvChipClass
{
91 SysBusDeviceClass parent_class
;
94 PnvChipType chip_type
;
95 uint64_t chip_cfam_id
;
100 DeviceRealize parent_realize
;
102 uint32_t (*core_pir
)(PnvChip
*chip
, uint32_t core_id
);
103 void (*intc_create
)(PnvChip
*chip
, PowerPCCPU
*cpu
, Error
**errp
);
104 ISABus
*(*isa_create
)(PnvChip
*chip
, Error
**errp
);
105 void (*dt_populate
)(PnvChip
*chip
, void *fdt
);
106 void (*pic_print_info
)(PnvChip
*chip
, Monitor
*mon
);
109 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
110 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
112 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
113 #define PNV_CHIP_POWER8E(obj) \
114 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
116 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
117 #define PNV_CHIP_POWER8(obj) \
118 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
120 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
121 #define PNV_CHIP_POWER8NVL(obj) \
122 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
124 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
125 #define PNV_CHIP_POWER9(obj) \
126 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
129 * This generates a HW chip id depending on an index, as found on a
130 * two socket system with dual chip modules :
132 * 0x0, 0x1, 0x10, 0x11
134 * 4 chips should be the maximum
136 * TODO: use a machine property to define the chip ids
138 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
141 * Converts back a HW chip id to an index. This is useful to calculate
142 * the MMIO addresses of some controllers which depend on the chip id.
144 #define PNV_CHIP_INDEX(chip) \
145 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
147 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
148 #define PNV_MACHINE(obj) \
149 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
151 typedef struct PnvMachineState
{
153 MachineState parent_obj
;
155 uint32_t initrd_base
;
162 uint32_t cpld_irqstate
;
165 Notifier powerdown_notifier
;
168 static inline bool pnv_chip_is_power9(const PnvChip
*chip
)
170 return PNV_CHIP_GET_CLASS(chip
)->chip_type
== PNV_CHIP_POWER9
;
173 static inline bool pnv_is_power9(PnvMachineState
*pnv
)
175 return pnv_chip_is_power9(pnv
->chips
[0]);
178 #define PNV_FDT_ADDR 0x01000000
179 #define PNV_TIMEBASE_FREQ 512000000ULL
184 void pnv_dt_bmc_sensors(IPMIBmc
*bmc
, void *fdt
);
185 void pnv_bmc_powerdown(IPMIBmc
*bmc
);
188 * POWER8 MMIO base addresses
190 #define PNV_XSCOM_SIZE 0x800000000ull
191 #define PNV_XSCOM_BASE(chip) \
192 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
195 * XSCOM 0x20109CA defines the ICP BAR:
197 * 0:29 : bits 14 to 43 of address to define 1 MB region.
198 * 30 : 1 to enable ICP to receive loads/stores against its BAR region
201 * Usually defined as :
203 * 0xffffe00200000000 -> 0x0003ffff80000000
204 * 0xffffe00600000000 -> 0x0003ffff80100000
205 * 0xffffe02200000000 -> 0x0003ffff80800000
206 * 0xffffe02600000000 -> 0x0003ffff80900000
208 #define PNV_ICP_SIZE 0x0000000000100000ull
209 #define PNV_ICP_BASE(chip) \
210 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
213 #define PNV_PSIHB_SIZE 0x0000000000100000ull
214 #define PNV_PSIHB_BASE(chip) \
215 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
217 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
218 #define PNV_PSIHB_FSP_BASE(chip) \
219 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
223 * POWER9 MMIO base addresses
225 #define PNV9_CHIP_BASE(chip, base) \
226 ((base) + ((uint64_t) (chip)->chip_id << 42))
228 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
229 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
231 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
232 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
234 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
235 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
237 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
238 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
241 #endif /* _PPC_PNV_H */