include/hw/ppc/pnv_lpc.h

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef _PPC_PNV_LPC_H
  20 #define _PPC_PNV_LPC_H
  21
  22 #include "hw/ppc/pnv_psi.h"
  23
  24 #define TYPE_PNV_LPC "pnv-lpc"
  25 #define PNV_LPC(obj) \
  26      OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
  27
  28 typedef struct PnvLpcController {
  29     DeviceState parent;
  30
  31     uint64_t eccb_stat_reg;
  32     uint32_t eccb_data_reg;
  33
  34     /* OPB bus */
  35     MemoryRegion opb_mr;
  36     AddressSpace opb_as;
  37
  38     /* ISA IO and Memory space */
  39     MemoryRegion isa_io;
  40     MemoryRegion isa_mem;
  41
  42     /* Windows from OPB to ISA (aliases) */
  43     MemoryRegion opb_isa_io;
  44     MemoryRegion opb_isa_mem;
  45     MemoryRegion opb_isa_fw;
  46
  47     /* Registers */
  48     MemoryRegion lpc_hc_regs;
  49     MemoryRegion opb_master_regs;
  50
  51     /* OPB Master LS registers */
  52     uint32_t opb_irq_stat;
  53     uint32_t opb_irq_mask;
  54     uint32_t opb_irq_pol;
  55     uint32_t opb_irq_input;
  56
  57     /* LPC HC registers */
  58     uint32_t lpc_hc_fw_seg_idsel;
  59     uint32_t lpc_hc_fw_rd_acc_size;
  60     uint32_t lpc_hc_irqser_ctrl;
  61     uint32_t lpc_hc_irqmask;
  62     uint32_t lpc_hc_irqstat;
  63     uint32_t lpc_hc_error_addr;
  64
  65     /* XSCOM registers */
  66     MemoryRegion xscom_regs;
  67
  68     /* PSI to generate interrupts */
  69     PnvPsi *psi;
  70 } PnvLpcController;
  71
  72 qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type,
  73                                  int nirqs);
  74
  75 #endif /* _PPC_PNV_LPC_H */