include/hw/ppc/pnv_xive.h

   1 /*
   2  * QEMU PowerPC XIVE interrupt controller model
   3  *
   4  * Copyright (c) 2017-2019, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef PPC_PNV_XIVE_H
  11 #define PPC_PNV_XIVE_H
  12
  13 #include "hw/ppc/xive.h"
  14 #include "qom/object.h"
  15 #include "hw/ppc/xive2.h"
  16
  17 struct PnvChip;
  18
  19 #define TYPE_PNV_XIVE "pnv-xive"
  20 OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass,
  21                     PNV_XIVE)
  22
  23 #define XIVE_BLOCK_MAX      16
  24
  25 #define XIVE_TABLE_BLK_MAX  16  /* Block Scope Table (0-15) */
  26 #define XIVE_TABLE_MIG_MAX  16  /* Migration Register Table (1-15) */
  27 #define XIVE_TABLE_VDT_MAX  16  /* VDT Domain Table (0-15) */
  28 #define XIVE_TABLE_EDT_MAX  64  /* EDT Domain Table (0-63) */
  29
  30 struct PnvXive {
  31     XiveRouter    parent_obj;
  32
  33     /* Owning chip */
  34     struct PnvChip *chip;
  35
  36     /* XSCOM addresses giving access to the controller registers */
  37     MemoryRegion  xscom_regs;
  38
  39     /* Main MMIO regions that can be configured by FW */
  40     MemoryRegion  ic_mmio;
  41     MemoryRegion    ic_reg_mmio;
  42     MemoryRegion    ic_notify_mmio;
  43     MemoryRegion    ic_lsi_mmio;
  44     MemoryRegion    tm_indirect_mmio;
  45     MemoryRegion  vc_mmio;
  46     MemoryRegion  pc_mmio;
  47     MemoryRegion  tm_mmio;
  48
  49     /*
  50      * IPI and END address spaces modeling the EDT segmentation in the
  51      * VC region
  52      */
  53     AddressSpace  ipi_as;
  54     MemoryRegion  ipi_mmio;
  55     MemoryRegion    ipi_edt_mmio;
  56
  57     AddressSpace  end_as;
  58     MemoryRegion  end_mmio;
  59     MemoryRegion    end_edt_mmio;
  60
  61     /* Shortcut values for the Main MMIO regions */
  62     hwaddr        ic_base;
  63     uint32_t      ic_shift;
  64     hwaddr        vc_base;
  65     uint32_t      vc_shift;
  66     hwaddr        pc_base;
  67     uint32_t      pc_shift;
  68     hwaddr        tm_base;
  69     uint32_t      tm_shift;
  70
  71     /* Our XIVE source objects for IPIs and ENDs */
  72     XiveSource    ipi_source;
  73     XiveENDSource end_source;
  74
  75     /* Interrupt controller registers */
  76     uint64_t      regs[0x300];
  77
  78     /*
  79      * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
  80      * These are in a SRAM protected by ECC.
  81      */
  82     uint64_t      vsds[5][XIVE_BLOCK_MAX];
  83
  84     /* Translation tables */
  85     uint64_t      blk[XIVE_TABLE_BLK_MAX];
  86     uint64_t      mig[XIVE_TABLE_MIG_MAX];
  87     uint64_t      vdt[XIVE_TABLE_VDT_MAX];
  88     uint64_t      edt[XIVE_TABLE_EDT_MAX];
  89 };
  90
  91 struct PnvXiveClass {
  92     XiveRouterClass parent_class;
  93
  94     DeviceRealize parent_realize;
  95 };
  96
  97 void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
  98
  99 /*
 100  * XIVE2 interrupt controller (POWER10)
 101  */
 102 #define TYPE_PNV_XIVE2 "pnv-xive2"
 103 OBJECT_DECLARE_TYPE(PnvXive2, PnvXive2Class, PNV_XIVE2);
 104
 105 typedef struct PnvXive2 {
 106     Xive2Router   parent_obj;
 107
 108     /* Owning chip */
 109     struct PnvChip *chip;
 110
 111     /* XSCOM addresses giving access to the controller registers */
 112     MemoryRegion  xscom_regs;
 113
 114     MemoryRegion  ic_mmio;
 115     MemoryRegion  ic_mmios[8];
 116     MemoryRegion  esb_mmio;
 117     MemoryRegion  end_mmio;
 118     MemoryRegion  nvc_mmio;
 119     MemoryRegion  nvpg_mmio;
 120     MemoryRegion  tm_mmio;
 121
 122     /* Shortcut values for the Main MMIO regions */
 123     hwaddr        ic_base;
 124     uint32_t      ic_shift;
 125     hwaddr        esb_base;
 126     uint32_t      esb_shift;
 127     hwaddr        end_base;
 128     uint32_t      end_shift;
 129     hwaddr        nvc_base;
 130     uint32_t      nvc_shift;
 131     hwaddr        nvpg_base;
 132     uint32_t      nvpg_shift;
 133     hwaddr        tm_base;
 134     uint32_t      tm_shift;
 135
 136     /* Interrupt controller registers */
 137     uint64_t      cq_regs[0x40];
 138     uint64_t      vc_regs[0x100];
 139     uint64_t      pc_regs[0x100];
 140     uint64_t      tctxt_regs[0x30];
 141
 142     /* To change default behavior */
 143     uint64_t      capabilities;
 144     uint64_t      config;
 145
 146     /* Our XIVE source objects for IPIs and ENDs */
 147     XiveSource    ipi_source;
 148     Xive2EndSource end_source;
 149
 150     /*
 151      * Virtual Structure Descriptor tables
 152      * These are in a SRAM protected by ECC.
 153      */
 154     uint64_t      vsds[9][XIVE_BLOCK_MAX];
 155
 156     /* Translation tables */
 157     uint64_t      tables[8][XIVE_BLOCK_MAX];
 158
 159 } PnvXive2;
 160
 161 typedef struct PnvXive2Class {
 162     Xive2RouterClass parent_class;
 163
 164     DeviceRealize parent_realize;
 165 } PnvXive2Class;
 166
 167 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon);
 168
 169 #endif /* PPC_PNV_XIVE_H */