4 #include "qemu/units.h"
5 #include "sysemu/dma.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10 #include "hw/ppc/spapr_irq.h"
11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */
12 #include "hw/ppc/xics.h" /* For ICSState */
18 typedef struct SpaprEventLogEntry SpaprEventLogEntry
;
19 typedef struct SpaprEventSource SpaprEventSource
;
20 typedef struct SpaprPendingHpt SpaprPendingHpt
;
22 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
23 #define SPAPR_ENTRY_POINT 0x100
25 #define SPAPR_TIMEBASE_FREQ 512000000ULL
27 #define TYPE_SPAPR_RTC "spapr-rtc"
29 #define SPAPR_RTC(obj) \
30 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC)
32 typedef struct SpaprRtcState SpaprRtcState
;
33 struct SpaprRtcState
{
35 DeviceState parent_obj
;
39 typedef struct SpaprDimmState SpaprDimmState
;
40 typedef struct SpaprMachineClass SpaprMachineClass
;
42 #define TYPE_SPAPR_MACHINE "spapr-machine"
43 #define SPAPR_MACHINE(obj) \
44 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE)
45 #define SPAPR_MACHINE_GET_CLASS(obj) \
46 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE)
47 #define SPAPR_MACHINE_CLASS(klass) \
48 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE)
51 SPAPR_RESIZE_HPT_DEFAULT
= 0,
52 SPAPR_RESIZE_HPT_DISABLED
,
53 SPAPR_RESIZE_HPT_ENABLED
,
54 SPAPR_RESIZE_HPT_REQUIRED
,
61 /* Hardware Transactional Memory */
62 #define SPAPR_CAP_HTM 0x00
63 /* Vector Scalar Extensions */
64 #define SPAPR_CAP_VSX 0x01
65 /* Decimal Floating Point */
66 #define SPAPR_CAP_DFP 0x02
67 /* Cache Flush on Privilege Change */
68 #define SPAPR_CAP_CFPC 0x03
69 /* Speculation Barrier Bounds Checking */
70 #define SPAPR_CAP_SBBC 0x04
71 /* Indirect Branch Serialisation */
72 #define SPAPR_CAP_IBS 0x05
73 /* HPT Maximum Page Size (encoded as a shift) */
74 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
76 #define SPAPR_CAP_NESTED_KVM_HV 0x07
77 /* Large Decrementer */
78 #define SPAPR_CAP_LARGE_DECREMENTER 0x08
79 /* Count Cache Flush Assist HW Instruction */
80 #define SPAPR_CAP_CCF_ASSIST 0x09
82 #define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1)
88 #define SPAPR_CAP_OFF 0x00
89 #define SPAPR_CAP_ON 0x01
94 #define SPAPR_CAP_BROKEN 0x00
95 #define SPAPR_CAP_WORKAROUND 0x01
96 #define SPAPR_CAP_FIXED 0x02
97 /* SPAPR_CAP_IBS (cap-ibs) */
98 #define SPAPR_CAP_FIXED_IBS 0x02
99 #define SPAPR_CAP_FIXED_CCD 0x03
100 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
102 typedef struct SpaprCapabilities SpaprCapabilities
;
103 struct SpaprCapabilities
{
104 uint8_t caps
[SPAPR_CAP_NUM
];
110 struct SpaprMachineClass
{
112 MachineClass parent_class
;
115 bool dr_lmb_enabled
; /* enable dynamic-reconfig/hotplug of LMBs */
116 bool dr_phb_enabled
; /* enable dynamic-reconfig/hotplug of PHBs */
117 bool update_dt_enabled
; /* enable KVMPPC_H_UPDATE_DT */
118 bool use_ohci_by_default
; /* use USB-OHCI instead of XHCI */
119 bool pre_2_10_has_unused_icps
;
120 bool legacy_irq_allocation
;
121 bool broken_host_serial_model
; /* present real host info to the guest */
122 bool pre_4_1_migration
; /* don't migrate hpt-max-page-size */
124 void (*phb_placement
)(SpaprMachineState
*spapr
, uint32_t index
,
125 uint64_t *buid
, hwaddr
*pio
,
126 hwaddr
*mmio32
, hwaddr
*mmio64
,
127 unsigned n_dma
, uint32_t *liobns
, hwaddr
*nv2gpa
,
128 hwaddr
*nv2atsd
, Error
**errp
);
129 SpaprResizeHpt resize_hpt_default
;
130 SpaprCapabilities default_caps
;
137 struct SpaprMachineState
{
139 MachineState parent_obj
;
141 struct SpaprVioBus
*vio_bus
;
142 QLIST_HEAD(, SpaprPhbState
) phbs
;
143 struct SpaprNvram
*nvram
;
147 SpaprResizeHpt resize_hpt
;
150 uint64_t patb_entry
; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
151 SpaprPendingHpt
*pending_hpt
; /* in-progress resize */
158 uint32_t fdt_initial_size
;
162 uint32_t initrd_base
;
164 uint64_t rtc_offset
; /* Now used only during incoming migration */
165 struct PPCTimebase tb
;
167 uint32_t vsmt
; /* Virtual SMT mode (KVM's "core stride") */
169 Notifier epow_notifier
;
170 QTAILQ_HEAD(, SpaprEventLogEntry
) pending_events
;
171 bool use_hotplug_event_source
;
172 SpaprEventSource
*event_sources
;
174 /* ibm,client-architecture-support option negotiation */
176 bool cas_legacy_guest_workaround
;
177 SpaprOptionVector
*ov5
; /* QEMU-supported option vectors */
178 SpaprOptionVector
*ov5_cas
; /* negotiated (via CAS) option vectors */
179 uint32_t max_compat_pvr
;
181 /* Migration state */
183 bool htab_first_pass
;
186 /* Pending DIMM unplug cache. It is populated when a LMB
187 * unplug starts. It can be regenerated if a migration
188 * occurs during the unplug process. */
189 QTAILQ_HEAD(, SpaprDimmState
) pending_dimm_unplugs
;
197 unsigned long *irq_map
;
202 bool cmd_line_caps
[SPAPR_CAP_NUM
];
203 SpaprCapabilities def
, eff
, mig
;
205 unsigned gpu_numa_id
;
209 #define H_BUSY 1 /* Hardware busy -- retry later */
210 #define H_CLOSED 2 /* Resource closed */
211 #define H_NOT_AVAILABLE 3
212 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
214 #define H_IN_PROGRESS 14 /* Kind of like busy */
215 #define H_PAGE_REGISTERED 15
216 #define H_PARTIAL_STORE 16
217 #define H_PENDING 17 /* returned from H_POLL_PENDING */
218 #define H_CONTINUE 18 /* Returned from H_Join on success */
219 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
220 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
221 is a good time to retry */
222 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
223 is a good time to retry */
224 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
225 is a good time to retry */
226 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
227 is a good time to retry */
228 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
229 is a good time to retry */
230 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
231 is a good time to retry */
232 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
233 #define H_HARDWARE -1 /* Hardware error */
234 #define H_FUNCTION -2 /* Function not supported */
235 #define H_PRIVILEGE -3 /* Caller not privileged */
236 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
237 #define H_BAD_MODE -5 /* Illegal msr value */
238 #define H_PTEG_FULL -6 /* PTEG is full */
239 #define H_NOT_FOUND -7 /* PTE was not found" */
240 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
242 #define H_AUTHORITY -10
243 #define H_PERMISSION -11
244 #define H_DROPPED -12
245 #define H_SOURCE_PARM -13
246 #define H_DEST_PARM -14
247 #define H_REMOTE_PARM -15
248 #define H_RESOURCE -16
249 #define H_ADAPTER_PARM -17
250 #define H_RH_PARM -18
251 #define H_RCQ_PARM -19
252 #define H_SCQ_PARM -20
253 #define H_EQ_PARM -21
254 #define H_RT_PARM -22
255 #define H_ST_PARM -23
256 #define H_SIGT_PARM -24
257 #define H_TOKEN_PARM -25
258 #define H_MLENGTH_PARM -27
259 #define H_MEM_PARM -28
260 #define H_MEM_ACCESS_PARM -29
261 #define H_ATTR_PARM -30
262 #define H_PORT_PARM -31
263 #define H_MCG_PARM -32
264 #define H_VL_PARM -33
265 #define H_TSIZE_PARM -34
266 #define H_TRACE_PARM -35
268 #define H_MASK_PARM -37
269 #define H_MCG_FULL -38
270 #define H_ALIAS_EXIST -39
271 #define H_P_COUNTER -40
272 #define H_TABLE_FULL -41
273 #define H_ALT_TABLE -42
274 #define H_MR_CONDITION -43
275 #define H_NOT_ENOUGH_RESOURCES -44
276 #define H_R_STATE -45
277 #define H_RESCINDEND -46
286 #define H_UNSUPPORTED_FLAG -256
287 #define H_MULTI_THREADS_ACTIVE -9005
290 /* Long Busy is a condition that can be returned by the firmware
291 * when a call cannot be completed now, but the identical call
292 * should be retried later. This prevents calls blocking in the
293 * firmware for long periods of time. Annoyingly the firmware can return
294 * a range of return codes, hinting at how long we should wait before
295 * retrying. If you don't care for the hint, the macro below is a good
296 * way to check for the long_busy return codes
298 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
299 && (x <= H_LONG_BUSY_END_RANGE))
302 #define H_LARGE_PAGE (1ULL<<(63-16))
303 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
304 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
305 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
306 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
307 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
308 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
309 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
310 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
311 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
312 #define H_ANDCOND (1ULL<<(63-33))
313 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
314 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
315 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
316 #define H_COPY_PAGE (1ULL<<(63-49))
317 #define H_N (1ULL<<(63-61))
318 #define H_PP1 (1ULL<<(63-62))
319 #define H_PP2 (1ULL<<(63-63))
321 /* Values for 2nd argument to H_SET_MODE */
322 #define H_SET_MODE_RESOURCE_SET_CIABR 1
323 #define H_SET_MODE_RESOURCE_SET_DAWR 2
324 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
325 #define H_SET_MODE_RESOURCE_LE 4
327 /* Flags for H_SET_MODE_RESOURCE_LE */
328 #define H_SET_MODE_ENDIAN_BIG 0
329 #define H_SET_MODE_ENDIAN_LITTLE 1
332 #define H_VASI_INVALID 0
333 #define H_VASI_ENABLED 1
334 #define H_VASI_ABORTED 2
335 #define H_VASI_SUSPENDING 3
336 #define H_VASI_SUSPENDED 4
337 #define H_VASI_RESUMED 5
338 #define H_VASI_COMPLETED 6
341 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
342 #define H_DABRX_KERNEL (1ULL<<(63-62))
343 #define H_DABRX_USER (1ULL<<(63-63))
345 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
346 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
347 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
348 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
349 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
350 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
351 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
352 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
353 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
354 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
355 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
356 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
357 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
358 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
360 /* Each control block has to be on a 4K boundary */
361 #define H_CB_ALIGNMENT 4096
363 /* pSeries hypervisor opcodes */
364 #define H_REMOVE 0x04
367 #define H_CLEAR_MOD 0x10
368 #define H_CLEAR_REF 0x14
369 #define H_PROTECT 0x18
370 #define H_GET_TCE 0x1c
371 #define H_PUT_TCE 0x20
372 #define H_SET_SPRG0 0x24
373 #define H_SET_DABR 0x28
374 #define H_PAGE_INIT 0x2c
375 #define H_SET_ASR 0x30
376 #define H_ASR_ON 0x34
377 #define H_ASR_OFF 0x38
378 #define H_LOGICAL_CI_LOAD 0x3c
379 #define H_LOGICAL_CI_STORE 0x40
380 #define H_LOGICAL_CACHE_LOAD 0x44
381 #define H_LOGICAL_CACHE_STORE 0x48
382 #define H_LOGICAL_ICBI 0x4c
383 #define H_LOGICAL_DCBF 0x50
384 #define H_GET_TERM_CHAR 0x54
385 #define H_PUT_TERM_CHAR 0x58
386 #define H_REAL_TO_LOGICAL 0x5c
387 #define H_HYPERVISOR_DATA 0x60
393 #define H_PERFMON 0x7c
394 #define H_MIGRATE_DMA 0x78
395 #define H_REGISTER_VPA 0xDC
397 #define H_CONFER 0xE4
399 #define H_GET_PPP 0xEC
400 #define H_SET_PPP 0xF0
403 #define H_REG_CRQ 0xFC
404 #define H_FREE_CRQ 0x100
405 #define H_VIO_SIGNAL 0x104
406 #define H_SEND_CRQ 0x108
407 #define H_COPY_RDMA 0x110
408 #define H_REGISTER_LOGICAL_LAN 0x114
409 #define H_FREE_LOGICAL_LAN 0x118
410 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
411 #define H_SEND_LOGICAL_LAN 0x120
412 #define H_BULK_REMOVE 0x124
413 #define H_MULTICAST_CTRL 0x130
414 #define H_SET_XDABR 0x134
415 #define H_STUFF_TCE 0x138
416 #define H_PUT_TCE_INDIRECT 0x13C
417 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
418 #define H_VTERM_PARTNER_INFO 0x150
419 #define H_REGISTER_VTERM 0x154
420 #define H_FREE_VTERM 0x158
421 #define H_RESET_EVENTS 0x15C
422 #define H_ALLOC_RESOURCE 0x160
423 #define H_FREE_RESOURCE 0x164
424 #define H_MODIFY_QP 0x168
425 #define H_QUERY_QP 0x16C
426 #define H_REREGISTER_PMR 0x170
427 #define H_REGISTER_SMR 0x174
428 #define H_QUERY_MR 0x178
429 #define H_QUERY_MW 0x17C
430 #define H_QUERY_HCA 0x180
431 #define H_QUERY_PORT 0x184
432 #define H_MODIFY_PORT 0x188
433 #define H_DEFINE_AQP1 0x18C
434 #define H_GET_TRACE_BUFFER 0x190
435 #define H_DEFINE_AQP0 0x194
436 #define H_RESIZE_MR 0x198
437 #define H_ATTACH_MCQP 0x19C
438 #define H_DETACH_MCQP 0x1A0
439 #define H_CREATE_RPT 0x1A4
440 #define H_REMOVE_RPT 0x1A8
441 #define H_REGISTER_RPAGES 0x1AC
442 #define H_DISABLE_AND_GETC 0x1B0
443 #define H_ERROR_DATA 0x1B4
444 #define H_GET_HCA_INFO 0x1B8
445 #define H_GET_PERF_COUNT 0x1BC
446 #define H_MANAGE_TRACE 0x1C0
447 #define H_GET_CPU_CHARACTERISTICS 0x1C8
448 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
449 #define H_QUERY_INT_STATE 0x1E4
450 #define H_POLL_PENDING 0x1D8
451 #define H_ILLAN_ATTRIBUTES 0x244
452 #define H_MODIFY_HEA_QP 0x250
453 #define H_QUERY_HEA_QP 0x254
454 #define H_QUERY_HEA 0x258
455 #define H_QUERY_HEA_PORT 0x25C
456 #define H_MODIFY_HEA_PORT 0x260
457 #define H_REG_BCMC 0x264
458 #define H_DEREG_BCMC 0x268
459 #define H_REGISTER_HEA_RPAGES 0x26C
460 #define H_DISABLE_AND_GET_HEA 0x270
461 #define H_GET_HEA_INFO 0x274
462 #define H_ALLOC_HEA_RESOURCE 0x278
463 #define H_ADD_CONN 0x284
464 #define H_DEL_CONN 0x288
466 #define H_VASI_STATE 0x2A4
467 #define H_ENABLE_CRQ 0x2B0
468 #define H_GET_EM_PARMS 0x2B8
469 #define H_SET_MPP 0x2D0
470 #define H_GET_MPP 0x2D4
471 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
472 #define H_XIRR_X 0x2FC
473 #define H_RANDOM 0x300
474 #define H_SET_MODE 0x31C
475 #define H_RESIZE_HPT_PREPARE 0x36C
476 #define H_RESIZE_HPT_COMMIT 0x370
477 #define H_CLEAN_SLB 0x374
478 #define H_INVALIDATE_PID 0x378
479 #define H_REGISTER_PROC_TBL 0x37C
480 #define H_SIGNAL_SYS_RESET 0x380
482 #define H_INT_GET_SOURCE_INFO 0x3A8
483 #define H_INT_SET_SOURCE_CONFIG 0x3AC
484 #define H_INT_GET_SOURCE_CONFIG 0x3B0
485 #define H_INT_GET_QUEUE_INFO 0x3B4
486 #define H_INT_SET_QUEUE_CONFIG 0x3B8
487 #define H_INT_GET_QUEUE_CONFIG 0x3BC
488 #define H_INT_SET_OS_REPORTING_LINE 0x3C0
489 #define H_INT_GET_OS_REPORTING_LINE 0x3C4
490 #define H_INT_ESB 0x3C8
491 #define H_INT_SYNC 0x3CC
492 #define H_INT_RESET 0x3D0
494 #define MAX_HCALL_OPCODE H_INT_RESET
496 /* The hcalls above are standardized in PAPR and implemented by pHyp
499 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
500 * We put those into the 0xf000-0xfffc range which is reserved by PAPR
501 * for "platform-specific" hcalls.
503 #define KVMPPC_HCALL_BASE 0xf000
504 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
505 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
506 /* Client Architecture support */
507 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
508 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
509 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT
511 typedef struct SpaprDeviceTreeUpdateHeader
{
513 } SpaprDeviceTreeUpdateHeader
;
515 #define hcall_dprintf(fmt, ...) \
517 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
520 typedef target_ulong (*spapr_hcall_fn
)(PowerPCCPU
*cpu
, SpaprMachineState
*sm
,
524 void spapr_register_hypercall(target_ulong opcode
, spapr_hcall_fn fn
);
525 target_ulong
spapr_hypercall(PowerPCCPU
*cpu
, target_ulong opcode
,
528 /* ibm,set-eeh-option */
529 #define RTAS_EEH_DISABLE 0
530 #define RTAS_EEH_ENABLE 1
531 #define RTAS_EEH_THAW_IO 2
532 #define RTAS_EEH_THAW_DMA 3
534 /* ibm,get-config-addr-info2 */
535 #define RTAS_GET_PE_ADDR 0
536 #define RTAS_GET_PE_MODE 1
537 #define RTAS_PE_MODE_NONE 0
538 #define RTAS_PE_MODE_NOT_SHARED 1
539 #define RTAS_PE_MODE_SHARED 2
541 /* ibm,read-slot-reset-state2 */
542 #define RTAS_EEH_PE_STATE_NORMAL 0
543 #define RTAS_EEH_PE_STATE_RESET 1
544 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
545 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4
546 #define RTAS_EEH_PE_STATE_UNAVAIL 5
547 #define RTAS_EEH_NOT_SUPPORT 0
548 #define RTAS_EEH_SUPPORT 1
549 #define RTAS_EEH_PE_UNAVAIL_INFO 1000
550 #define RTAS_EEH_PE_RECOVER_INFO 0
552 /* ibm,set-slot-reset */
553 #define RTAS_SLOT_RESET_DEACTIVATE 0
554 #define RTAS_SLOT_RESET_HOT 1
555 #define RTAS_SLOT_RESET_FUNDAMENTAL 3
557 /* ibm,slot-error-detail */
558 #define RTAS_SLOT_TEMP_ERR_LOG 1
559 #define RTAS_SLOT_PERM_ERR_LOG 2
561 /* RTAS return codes */
562 #define RTAS_OUT_SUCCESS 0
563 #define RTAS_OUT_NO_ERRORS_FOUND 1
564 #define RTAS_OUT_HW_ERROR -1
565 #define RTAS_OUT_BUSY -2
566 #define RTAS_OUT_PARAM_ERROR -3
567 #define RTAS_OUT_NOT_SUPPORTED -3
568 #define RTAS_OUT_NO_SUCH_INDICATOR -3
569 #define RTAS_OUT_NOT_AUTHORIZED -9002
570 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
572 /* DDW pagesize mask values from ibm,query-pe-dma-window */
573 #define RTAS_DDW_PGSIZE_4K 0x01
574 #define RTAS_DDW_PGSIZE_64K 0x02
575 #define RTAS_DDW_PGSIZE_16M 0x04
576 #define RTAS_DDW_PGSIZE_32M 0x08
577 #define RTAS_DDW_PGSIZE_64M 0x10
578 #define RTAS_DDW_PGSIZE_128M 0x20
579 #define RTAS_DDW_PGSIZE_256M 0x40
580 #define RTAS_DDW_PGSIZE_16G 0x80
583 #define RTAS_TOKEN_BASE 0x2000
585 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
586 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
587 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
588 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
589 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
590 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
591 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
592 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
593 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
594 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
595 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
596 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
597 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
598 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
599 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
600 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
601 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
602 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
603 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
604 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
605 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
606 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
607 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
608 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
609 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
610 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
611 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
612 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
613 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
614 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
615 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
616 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
617 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
618 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
619 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
620 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
621 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
622 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
623 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
624 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
625 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
626 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
628 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A)
630 /* RTAS ibm,get-system-parameter token values */
631 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
632 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
633 #define RTAS_SYSPARM_UUID 48
635 /* RTAS indicator/sensor types
637 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
639 * NOTE: currently only DR-related sensors are implemented here
641 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
642 #define RTAS_SENSOR_TYPE_DR 9002
643 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
644 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
646 /* Possible values for the platform-processor-diagnostics-run-mode parameter
647 * of the RTAS ibm,get-system-parameter call.
649 #define DIAGNOSTICS_RUN_MODE_DISABLED 0
650 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
651 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
652 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
654 static inline uint64_t ppc64_phys_to_real(uint64_t addr
)
656 return addr
& ~0xF000000000000000ULL
;
659 static inline uint32_t rtas_ld(target_ulong phys
, int n
)
661 return ldl_be_phys(&address_space_memory
, ppc64_phys_to_real(phys
+ 4*n
));
664 static inline uint64_t rtas_ldq(target_ulong phys
, int n
)
666 return (uint64_t)rtas_ld(phys
, n
) << 32 | rtas_ld(phys
, n
+ 1);
669 static inline void rtas_st(target_ulong phys
, int n
, uint32_t val
)
671 stl_be_phys(&address_space_memory
, ppc64_phys_to_real(phys
+ 4*n
), val
);
674 typedef void (*spapr_rtas_fn
)(PowerPCCPU
*cpu
, SpaprMachineState
*sm
,
676 uint32_t nargs
, target_ulong args
,
677 uint32_t nret
, target_ulong rets
);
678 void spapr_rtas_register(int token
, const char *name
, spapr_rtas_fn fn
);
679 target_ulong
spapr_rtas_call(PowerPCCPU
*cpu
, SpaprMachineState
*sm
,
680 uint32_t token
, uint32_t nargs
, target_ulong args
,
681 uint32_t nret
, target_ulong rets
);
682 void spapr_dt_rtas_tokens(void *fdt
, int rtas
);
683 void spapr_load_rtas(SpaprMachineState
*spapr
, void *fdt
, hwaddr addr
);
685 #define SPAPR_TCE_PAGE_SHIFT 12
686 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
687 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
689 #define SPAPR_VIO_BASE_LIOBN 0x00000000
690 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
691 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
692 (0x80000000 | ((phb_index) << 8) | (window_num))
693 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
694 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
696 #define RTAS_ERROR_LOG_MAX 2048
698 #define RTAS_EVENT_SCAN_RATE 1
700 /* This helper should be used to encode interrupt specifiers when the related
701 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
702 * VIO devices, RTAS event sources and PHBs).
704 static inline void spapr_dt_irq(uint32_t *intspec
, int irq
, bool is_lsi
)
706 intspec
[0] = cpu_to_be32(irq
);
707 intspec
[1] = is_lsi
? cpu_to_be32(1) : 0;
710 typedef struct SpaprTceTable SpaprTceTable
;
712 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
713 #define SPAPR_TCE_TABLE(obj) \
714 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE)
716 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
717 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
718 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
720 struct SpaprTceTable
{
727 uint32_t mig_nb_table
;
731 bool skipping_replay
;
734 IOMMUMemoryRegion iommu
;
735 struct SpaprVioDevice
*vdev
; /* for @bypass migration compatibility only */
736 QLIST_ENTRY(SpaprTceTable
) list
;
739 SpaprTceTable
*spapr_tce_find_by_liobn(target_ulong liobn
);
741 struct SpaprEventLogEntry
{
743 uint32_t extended_length
;
745 QTAILQ_ENTRY(SpaprEventLogEntry
) next
;
748 void spapr_events_init(SpaprMachineState
*sm
);
749 void spapr_dt_events(SpaprMachineState
*sm
, void *fdt
);
750 int spapr_h_cas_compose_response(SpaprMachineState
*sm
,
751 target_ulong addr
, target_ulong size
,
752 SpaprOptionVector
*ov5_updates
);
753 void close_htab_fd(SpaprMachineState
*spapr
);
754 void spapr_setup_hpt_and_vrma(SpaprMachineState
*spapr
);
755 void spapr_free_hpt(SpaprMachineState
*spapr
);
756 SpaprTceTable
*spapr_tce_new_table(DeviceState
*owner
, uint32_t liobn
);
757 void spapr_tce_table_enable(SpaprTceTable
*tcet
,
758 uint32_t page_shift
, uint64_t bus_offset
,
760 void spapr_tce_table_disable(SpaprTceTable
*tcet
);
761 void spapr_tce_set_need_vfio(SpaprTceTable
*tcet
, bool need_vfio
);
763 MemoryRegion
*spapr_tce_get_iommu(SpaprTceTable
*tcet
);
764 int spapr_dma_dt(void *fdt
, int node_off
, const char *propname
,
765 uint32_t liobn
, uint64_t window
, uint32_t size
);
766 int spapr_tcet_dma_dt(void *fdt
, int node_off
, const char *propname
,
767 SpaprTceTable
*tcet
);
768 void spapr_pci_switch_vga(bool big_endian
);
769 void spapr_hotplug_req_add_by_index(SpaprDrc
*drc
);
770 void spapr_hotplug_req_remove_by_index(SpaprDrc
*drc
);
771 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type
,
773 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type
,
775 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type
,
776 uint32_t count
, uint32_t index
);
777 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type
,
778 uint32_t count
, uint32_t index
);
779 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
);
780 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
782 void spapr_clear_pending_events(SpaprMachineState
*spapr
);
783 int spapr_max_server_number(SpaprMachineState
*spapr
);
784 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
785 uint64_t pte0
, uint64_t pte1
);
788 void spapr_core_release(DeviceState
*dev
);
789 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
790 void *fdt
, int *fdt_start_offset
, Error
**errp
);
791 void spapr_lmb_release(DeviceState
*dev
);
792 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
793 void *fdt
, int *fdt_start_offset
, Error
**errp
);
794 void spapr_phb_release(DeviceState
*dev
);
795 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
796 void *fdt
, int *fdt_start_offset
, Error
**errp
);
798 void spapr_rtc_read(SpaprRtcState
*rtc
, struct tm
*tm
, uint32_t *ns
);
799 int spapr_rtc_import_offset(SpaprRtcState
*rtc
, int64_t legacy_offset
);
801 #define TYPE_SPAPR_RNG "spapr-rng"
803 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
806 * This defines the maximum number of DIMM slots we can have for sPAPR
807 * guest. This is not defined by sPAPR but we are defining it to 32 slots
808 * based on default number of slots provided by PowerPC kernel.
810 #define SPAPR_MAX_RAM_SLOTS 32
812 /* 1GB alignment for hotplug memory region */
813 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
816 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
817 * property under ibm,dynamic-reconfiguration-memory node.
819 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
822 * Defines for flag value in ibm,dynamic-memory property under
823 * ibm,dynamic-reconfiguration-memory node.
825 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
826 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
827 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
829 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
);
831 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
833 int spapr_get_vcpu_id(PowerPCCPU
*cpu
);
834 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
);
835 PowerPCCPU
*spapr_find_cpu(int vcpu_id
);
837 int spapr_caps_pre_load(void *opaque
);
838 int spapr_caps_pre_save(void *opaque
);
841 * Handling of optional capabilities
843 extern const VMStateDescription vmstate_spapr_cap_htm
;
844 extern const VMStateDescription vmstate_spapr_cap_vsx
;
845 extern const VMStateDescription vmstate_spapr_cap_dfp
;
846 extern const VMStateDescription vmstate_spapr_cap_cfpc
;
847 extern const VMStateDescription vmstate_spapr_cap_sbbc
;
848 extern const VMStateDescription vmstate_spapr_cap_ibs
;
849 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize
;
850 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv
;
851 extern const VMStateDescription vmstate_spapr_cap_large_decr
;
852 extern const VMStateDescription vmstate_spapr_cap_ccf_assist
;
854 static inline uint8_t spapr_get_cap(SpaprMachineState
*spapr
, int cap
)
856 return spapr
->eff
.caps
[cap
];
859 void spapr_caps_init(SpaprMachineState
*spapr
);
860 void spapr_caps_apply(SpaprMachineState
*spapr
);
861 void spapr_caps_cpu_apply(SpaprMachineState
*spapr
, PowerPCCPU
*cpu
);
862 void spapr_caps_add_properties(SpaprMachineClass
*smc
, Error
**errp
);
863 int spapr_caps_post_migration(SpaprMachineState
*spapr
);
865 void spapr_check_pagesize(SpaprMachineState
*spapr
, hwaddr pagesize
,
870 #define SPAPR_OV5_XIVE_LEGACY 0x0
871 #define SPAPR_OV5_XIVE_EXPLOIT 0x40
872 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */
874 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
);
875 #endif /* HW_SPAPR_H */