include/hw/ppc/spapr.h

   1 #ifndef HW_SPAPR_H
   2 #define HW_SPAPR_H
   3
   4 #include "sysemu/dma.h"
   5 #include "hw/boards.h"
   6 #include "hw/ppc/xics.h"
   7 #include "hw/ppc/spapr_drc.h"
   8 #include "hw/mem/pc-dimm.h"
   9 #include "hw/ppc/spapr_ovec.h"
  10
  11 struct VIOsPAPRBus;
  12 struct sPAPRPHBState;
  13 struct sPAPRNVRAM;
  14 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
  15 typedef struct sPAPREventSource sPAPREventSource;
  16
  17 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  18 #define SPAPR_ENTRY_POINT       0x100
  19
  20 #define SPAPR_TIMEBASE_FREQ     512000000ULL
  21
  22 #define TYPE_SPAPR_RTC "spapr-rtc"
  23
  24 #define SPAPR_RTC(obj)                                  \
  25     OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
  26
  27 typedef struct sPAPRRTCState sPAPRRTCState;
  28 struct sPAPRRTCState {
  29     /*< private >*/
  30     DeviceState parent_obj;
  31     int64_t ns_offset;
  32 };
  33
  34 typedef struct sPAPRDIMMState sPAPRDIMMState;
  35 typedef struct sPAPRMachineClass sPAPRMachineClass;
  36
  37 #define TYPE_SPAPR_MACHINE      "spapr-machine"
  38 #define SPAPR_MACHINE(obj) \
  39     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
  40 #define SPAPR_MACHINE_GET_CLASS(obj) \
  41     OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
  42 #define SPAPR_MACHINE_CLASS(klass) \
  43     OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
  44
  45 /**
  46  * sPAPRMachineClass:
  47  */
  48 struct sPAPRMachineClass {
  49     /*< private >*/
  50     MachineClass parent_class;
  51
  52     /*< public >*/
  53     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
  54     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
  55     const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */
  56     bool pre_2_10_has_unused_icps;
  57     void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
  58                           uint64_t *buid, hwaddr *pio,
  59                           hwaddr *mmio32, hwaddr *mmio64,
  60                           unsigned n_dma, uint32_t *liobns, Error **errp);
  61 };
  62
  63 /**
  64  * sPAPRMachineState:
  65  */
  66 struct sPAPRMachineState {
  67     /*< private >*/
  68     MachineState parent_obj;
  69
  70     struct VIOsPAPRBus *vio_bus;
  71     QLIST_HEAD(, sPAPRPHBState) phbs;
  72     struct sPAPRNVRAM *nvram;
  73     ICSState *ics;
  74     sPAPRRTCState rtc;
  75
  76     void *htab;
  77     uint32_t htab_shift;
  78     uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
  79     hwaddr rma_size;
  80     int vrma_adjust;
  81     ssize_t rtas_size;
  82     void *rtas_blob;
  83     long kernel_size;
  84     bool kernel_le;
  85     uint32_t initrd_base;
  86     long initrd_size;
  87     uint64_t rtc_offset; /* Now used only during incoming migration */
  88     struct PPCTimebase tb;
  89     bool has_graphics;
  90
  91     Notifier epow_notifier;
  92     QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
  93     bool use_hotplug_event_source;
  94     sPAPREventSource *event_sources;
  95
  96     /* ibm,client-architecture-support option negotiation */
  97     bool cas_reboot;
  98     bool cas_legacy_guest_workaround;
  99     sPAPROptionVector *ov5;         /* QEMU-supported option vectors */
 100     sPAPROptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
 101     uint32_t max_compat_pvr;
 102
 103     /* Migration state */
 104     int htab_save_index;
 105     bool htab_first_pass;
 106     int htab_fd;
 107
 108     /* Pending DIMM unplug cache. It is populated when a LMB
 109      * unplug starts. It can be regenerated if a migration
 110      * occurs during the unplug process. */
 111     QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs;
 112
 113     /*< public >*/
 114     char *kvm_type;
 115     MemoryHotplugState hotplug_memory;
 116
 117     const char *icp_type;
 118 };
 119
 120 #define H_SUCCESS         0
 121 #define H_BUSY            1        /* Hardware busy -- retry later */
 122 #define H_CLOSED          2        /* Resource closed */
 123 #define H_NOT_AVAILABLE   3
 124 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
 125 #define H_PARTIAL         5
 126 #define H_IN_PROGRESS     14       /* Kind of like busy */
 127 #define H_PAGE_REGISTERED 15
 128 #define H_PARTIAL_STORE   16
 129 #define H_PENDING         17       /* returned from H_POLL_PENDING */
 130 #define H_CONTINUE        18       /* Returned from H_Join on success */
 131 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
 132 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
 133                                                  is a good time to retry */
 134 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
 135                                                  is a good time to retry */
 136 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
 137                                                  is a good time to retry */
 138 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
 139                                                  is a good time to retry */
 140 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
 141                                                  is a good time to retry */
 142 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
 143                                                  is a good time to retry */
 144 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
 145 #define H_HARDWARE        -1       /* Hardware error */
 146 #define H_FUNCTION        -2       /* Function not supported */
 147 #define H_PRIVILEGE       -3       /* Caller not privileged */
 148 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
 149 #define H_BAD_MODE        -5       /* Illegal msr value */
 150 #define H_PTEG_FULL       -6       /* PTEG is full */
 151 #define H_NOT_FOUND       -7       /* PTE was not found" */
 152 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
 153 #define H_NO_MEM          -9
 154 #define H_AUTHORITY       -10
 155 #define H_PERMISSION      -11
 156 #define H_DROPPED         -12
 157 #define H_SOURCE_PARM     -13
 158 #define H_DEST_PARM       -14
 159 #define H_REMOTE_PARM     -15
 160 #define H_RESOURCE        -16
 161 #define H_ADAPTER_PARM    -17
 162 #define H_RH_PARM         -18
 163 #define H_RCQ_PARM        -19
 164 #define H_SCQ_PARM        -20
 165 #define H_EQ_PARM         -21
 166 #define H_RT_PARM         -22
 167 #define H_ST_PARM         -23
 168 #define H_SIGT_PARM       -24
 169 #define H_TOKEN_PARM      -25
 170 #define H_MLENGTH_PARM    -27
 171 #define H_MEM_PARM        -28
 172 #define H_MEM_ACCESS_PARM -29
 173 #define H_ATTR_PARM       -30
 174 #define H_PORT_PARM       -31
 175 #define H_MCG_PARM        -32
 176 #define H_VL_PARM         -33
 177 #define H_TSIZE_PARM      -34
 178 #define H_TRACE_PARM      -35
 179
 180 #define H_MASK_PARM       -37
 181 #define H_MCG_FULL        -38
 182 #define H_ALIAS_EXIST     -39
 183 #define H_P_COUNTER       -40
 184 #define H_TABLE_FULL      -41
 185 #define H_ALT_TABLE       -42
 186 #define H_MR_CONDITION    -43
 187 #define H_NOT_ENOUGH_RESOURCES -44
 188 #define H_R_STATE         -45
 189 #define H_RESCINDEND      -46
 190 #define H_P2              -55
 191 #define H_P3              -56
 192 #define H_P4              -57
 193 #define H_P5              -58
 194 #define H_P6              -59
 195 #define H_P7              -60
 196 #define H_P8              -61
 197 #define H_P9              -62
 198 #define H_UNSUPPORTED_FLAG -256
 199 #define H_MULTI_THREADS_ACTIVE -9005
 200
 201
 202 /* Long Busy is a condition that can be returned by the firmware
 203  * when a call cannot be completed now, but the identical call
 204  * should be retried later.  This prevents calls blocking in the
 205  * firmware for long periods of time.  Annoyingly the firmware can return
 206  * a range of return codes, hinting at how long we should wait before
 207  * retrying.  If you don't care for the hint, the macro below is a good
 208  * way to check for the long_busy return codes
 209  */
 210 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 211                             && (x <= H_LONG_BUSY_END_RANGE))
 212
 213 /* Flags */
 214 #define H_LARGE_PAGE      (1ULL<<(63-16))
 215 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 216 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 217 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 218 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 219 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 220 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 221 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 222 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 223 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 224 #define H_ANDCOND         (1ULL<<(63-33))
 225 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 226 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 227 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 228 #define H_COPY_PAGE       (1ULL<<(63-49))
 229 #define H_N               (1ULL<<(63-61))
 230 #define H_PP1             (1ULL<<(63-62))
 231 #define H_PP2             (1ULL<<(63-63))
 232
 233 /* Values for 2nd argument to H_SET_MODE */
 234 #define H_SET_MODE_RESOURCE_SET_CIABR           1
 235 #define H_SET_MODE_RESOURCE_SET_DAWR            2
 236 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 237 #define H_SET_MODE_RESOURCE_LE                  4
 238
 239 /* Flags for H_SET_MODE_RESOURCE_LE */
 240 #define H_SET_MODE_ENDIAN_BIG    0
 241 #define H_SET_MODE_ENDIAN_LITTLE 1
 242
 243 /* VASI States */
 244 #define H_VASI_INVALID    0
 245 #define H_VASI_ENABLED    1
 246 #define H_VASI_ABORTED    2
 247 #define H_VASI_SUSPENDING 3
 248 #define H_VASI_SUSPENDED  4
 249 #define H_VASI_RESUMED    5
 250 #define H_VASI_COMPLETED  6
 251
 252 /* DABRX flags */
 253 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 254 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 255 #define H_DABRX_USER       (1ULL<<(63-63))
 256
 257 /* Each control block has to be on a 4K boundary */
 258 #define H_CB_ALIGNMENT     4096
 259
 260 /* pSeries hypervisor opcodes */
 261 #define H_REMOVE                0x04
 262 #define H_ENTER                 0x08
 263 #define H_READ                  0x0c
 264 #define H_CLEAR_MOD             0x10
 265 #define H_CLEAR_REF             0x14
 266 #define H_PROTECT               0x18
 267 #define H_GET_TCE               0x1c
 268 #define H_PUT_TCE               0x20
 269 #define H_SET_SPRG0             0x24
 270 #define H_SET_DABR              0x28
 271 #define H_PAGE_INIT             0x2c
 272 #define H_SET_ASR               0x30
 273 #define H_ASR_ON                0x34
 274 #define H_ASR_OFF               0x38
 275 #define H_LOGICAL_CI_LOAD       0x3c
 276 #define H_LOGICAL_CI_STORE      0x40
 277 #define H_LOGICAL_CACHE_LOAD    0x44
 278 #define H_LOGICAL_CACHE_STORE   0x48
 279 #define H_LOGICAL_ICBI          0x4c
 280 #define H_LOGICAL_DCBF          0x50
 281 #define H_GET_TERM_CHAR         0x54
 282 #define H_PUT_TERM_CHAR         0x58
 283 #define H_REAL_TO_LOGICAL       0x5c
 284 #define H_HYPERVISOR_DATA       0x60
 285 #define H_EOI                   0x64
 286 #define H_CPPR                  0x68
 287 #define H_IPI                   0x6c
 288 #define H_IPOLL                 0x70
 289 #define H_XIRR                  0x74
 290 #define H_PERFMON               0x7c
 291 #define H_MIGRATE_DMA           0x78
 292 #define H_REGISTER_VPA          0xDC
 293 #define H_CEDE                  0xE0
 294 #define H_CONFER                0xE4
 295 #define H_PROD                  0xE8
 296 #define H_GET_PPP               0xEC
 297 #define H_SET_PPP               0xF0
 298 #define H_PURR                  0xF4
 299 #define H_PIC                   0xF8
 300 #define H_REG_CRQ               0xFC
 301 #define H_FREE_CRQ              0x100
 302 #define H_VIO_SIGNAL            0x104
 303 #define H_SEND_CRQ              0x108
 304 #define H_COPY_RDMA             0x110
 305 #define H_REGISTER_LOGICAL_LAN  0x114
 306 #define H_FREE_LOGICAL_LAN      0x118
 307 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 308 #define H_SEND_LOGICAL_LAN      0x120
 309 #define H_BULK_REMOVE           0x124
 310 #define H_MULTICAST_CTRL        0x130
 311 #define H_SET_XDABR             0x134
 312 #define H_STUFF_TCE             0x138
 313 #define H_PUT_TCE_INDIRECT      0x13C
 314 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 315 #define H_VTERM_PARTNER_INFO    0x150
 316 #define H_REGISTER_VTERM        0x154
 317 #define H_FREE_VTERM            0x158
 318 #define H_RESET_EVENTS          0x15C
 319 #define H_ALLOC_RESOURCE        0x160
 320 #define H_FREE_RESOURCE         0x164
 321 #define H_MODIFY_QP             0x168
 322 #define H_QUERY_QP              0x16C
 323 #define H_REREGISTER_PMR        0x170
 324 #define H_REGISTER_SMR          0x174
 325 #define H_QUERY_MR              0x178
 326 #define H_QUERY_MW              0x17C
 327 #define H_QUERY_HCA             0x180
 328 #define H_QUERY_PORT            0x184
 329 #define H_MODIFY_PORT           0x188
 330 #define H_DEFINE_AQP1           0x18C
 331 #define H_GET_TRACE_BUFFER      0x190
 332 #define H_DEFINE_AQP0           0x194
 333 #define H_RESIZE_MR             0x198
 334 #define H_ATTACH_MCQP           0x19C
 335 #define H_DETACH_MCQP           0x1A0
 336 #define H_CREATE_RPT            0x1A4
 337 #define H_REMOVE_RPT            0x1A8
 338 #define H_REGISTER_RPAGES       0x1AC
 339 #define H_DISABLE_AND_GETC      0x1B0
 340 #define H_ERROR_DATA            0x1B4
 341 #define H_GET_HCA_INFO          0x1B8
 342 #define H_GET_PERF_COUNT        0x1BC
 343 #define H_MANAGE_TRACE          0x1C0
 344 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 345 #define H_QUERY_INT_STATE       0x1E4
 346 #define H_POLL_PENDING          0x1D8
 347 #define H_ILLAN_ATTRIBUTES      0x244
 348 #define H_MODIFY_HEA_QP         0x250
 349 #define H_QUERY_HEA_QP          0x254
 350 #define H_QUERY_HEA             0x258
 351 #define H_QUERY_HEA_PORT        0x25C
 352 #define H_MODIFY_HEA_PORT       0x260
 353 #define H_REG_BCMC              0x264
 354 #define H_DEREG_BCMC            0x268
 355 #define H_REGISTER_HEA_RPAGES   0x26C
 356 #define H_DISABLE_AND_GET_HEA   0x270
 357 #define H_GET_HEA_INFO          0x274
 358 #define H_ALLOC_HEA_RESOURCE    0x278
 359 #define H_ADD_CONN              0x284
 360 #define H_DEL_CONN              0x288
 361 #define H_JOIN                  0x298
 362 #define H_VASI_STATE            0x2A4
 363 #define H_ENABLE_CRQ            0x2B0
 364 #define H_GET_EM_PARMS          0x2B8
 365 #define H_SET_MPP               0x2D0
 366 #define H_GET_MPP               0x2D4
 367 #define H_XIRR_X                0x2FC
 368 #define H_RANDOM                0x300
 369 #define H_SET_MODE              0x31C
 370 #define H_CLEAN_SLB             0x374
 371 #define H_INVALIDATE_PID        0x378
 372 #define H_REGISTER_PROC_TBL     0x37C
 373 #define H_SIGNAL_SYS_RESET      0x380
 374 #define MAX_HCALL_OPCODE        H_SIGNAL_SYS_RESET
 375
 376 /* The hcalls above are standardized in PAPR and implemented by pHyp
 377  * as well.
 378  *
 379  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 380  * So far we just need one for H_RTAS, but in future we'll need more
 381  * for extensions like virtio.  We put those into the 0xf000-0xfffc
 382  * range which is reserved by PAPR for "platform-specific" hcalls.
 383  */
 384 #define KVMPPC_HCALL_BASE       0xf000
 385 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 386 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 387 /* Client Architecture support */
 388 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 389 #define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
 390
 391 typedef struct sPAPRDeviceTreeUpdateHeader {
 392     uint32_t version_id;
 393 } sPAPRDeviceTreeUpdateHeader;
 394
 395 #define hcall_dprintf(fmt, ...) \
 396     do { \
 397         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
 398     } while (0)
 399
 400 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 401                                        target_ulong opcode,
 402                                        target_ulong *args);
 403
 404 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 405 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 406                              target_ulong *args);
 407
 408 /* ibm,set-eeh-option */
 409 #define RTAS_EEH_DISABLE                 0
 410 #define RTAS_EEH_ENABLE                  1
 411 #define RTAS_EEH_THAW_IO                 2
 412 #define RTAS_EEH_THAW_DMA                3
 413
 414 /* ibm,get-config-addr-info2 */
 415 #define RTAS_GET_PE_ADDR                 0
 416 #define RTAS_GET_PE_MODE                 1
 417 #define RTAS_PE_MODE_NONE                0
 418 #define RTAS_PE_MODE_NOT_SHARED          1
 419 #define RTAS_PE_MODE_SHARED              2
 420
 421 /* ibm,read-slot-reset-state2 */
 422 #define RTAS_EEH_PE_STATE_NORMAL         0
 423 #define RTAS_EEH_PE_STATE_RESET          1
 424 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
 425 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
 426 #define RTAS_EEH_PE_STATE_UNAVAIL        5
 427 #define RTAS_EEH_NOT_SUPPORT             0
 428 #define RTAS_EEH_SUPPORT                 1
 429 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
 430 #define RTAS_EEH_PE_RECOVER_INFO         0
 431
 432 /* ibm,set-slot-reset */
 433 #define RTAS_SLOT_RESET_DEACTIVATE       0
 434 #define RTAS_SLOT_RESET_HOT              1
 435 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
 436
 437 /* ibm,slot-error-detail */
 438 #define RTAS_SLOT_TEMP_ERR_LOG           1
 439 #define RTAS_SLOT_PERM_ERR_LOG           2
 440
 441 /* RTAS return codes */
 442 #define RTAS_OUT_SUCCESS                        0
 443 #define RTAS_OUT_NO_ERRORS_FOUND                1
 444 #define RTAS_OUT_HW_ERROR                       -1
 445 #define RTAS_OUT_BUSY                           -2
 446 #define RTAS_OUT_PARAM_ERROR                    -3
 447 #define RTAS_OUT_NOT_SUPPORTED                  -3
 448 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
 449 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
 450 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
 451
 452 /* DDW pagesize mask values from ibm,query-pe-dma-window */
 453 #define RTAS_DDW_PGSIZE_4K       0x01
 454 #define RTAS_DDW_PGSIZE_64K      0x02
 455 #define RTAS_DDW_PGSIZE_16M      0x04
 456 #define RTAS_DDW_PGSIZE_32M      0x08
 457 #define RTAS_DDW_PGSIZE_64M      0x10
 458 #define RTAS_DDW_PGSIZE_128M     0x20
 459 #define RTAS_DDW_PGSIZE_256M     0x40
 460 #define RTAS_DDW_PGSIZE_16G      0x80
 461
 462 /* RTAS tokens */
 463 #define RTAS_TOKEN_BASE      0x2000
 464
 465 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 466 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 467 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 468 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 469 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 470 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 471 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 472 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 473 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 474 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 475 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 476 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 477 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 478 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 479 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 480 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 481 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 482 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 483 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 484 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 485 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 486 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 487 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 488 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 489 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 490 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 491 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 492 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 493 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 494 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 495 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 496 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 497 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
 498 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
 499 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
 500 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
 501 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
 502 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
 503 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
 504 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
 505 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
 506 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
 507
 508 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2A)
 509
 510 /* RTAS ibm,get-system-parameter token values */
 511 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 512 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 513 #define RTAS_SYSPARM_UUID                        48
 514
 515 /* RTAS indicator/sensor types
 516  *
 517  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
 518  *
 519  * NOTE: currently only DR-related sensors are implemented here
 520  */
 521 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
 522 #define RTAS_SENSOR_TYPE_DR                     9002
 523 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
 524 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
 525
 526 /* Possible values for the platform-processor-diagnostics-run-mode parameter
 527  * of the RTAS ibm,get-system-parameter call.
 528  */
 529 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
 530 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 531 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 532 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 533
 534 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 535 {
 536     return addr & ~0xF000000000000000ULL;
 537 }
 538
 539 static inline uint32_t rtas_ld(target_ulong phys, int n)
 540 {
 541     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 542 }
 543
 544 static inline uint64_t rtas_ldq(target_ulong phys, int n)
 545 {
 546     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
 547 }
 548
 549 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 550 {
 551     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 552 }
 553
 554 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 555                               uint32_t token,
 556                               uint32_t nargs, target_ulong args,
 557                               uint32_t nret, target_ulong rets);
 558 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 559 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
 560                              uint32_t token, uint32_t nargs, target_ulong args,
 561                              uint32_t nret, target_ulong rets);
 562 void spapr_dt_rtas_tokens(void *fdt, int rtas);
 563 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
 564
 565 #define SPAPR_TCE_PAGE_SHIFT   12
 566 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 567 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 568
 569 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 570 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
 571 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
 572     (0x80000000 | ((phb_index) << 8) | (window_num))
 573 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
 574 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
 575
 576 #define RTAS_ERROR_LOG_MAX      2048
 577
 578 #define RTAS_EVENT_SCAN_RATE    1
 579
 580 typedef struct sPAPRTCETable sPAPRTCETable;
 581
 582 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 583 #define SPAPR_TCE_TABLE(obj) \
 584     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
 585
 586 struct sPAPRTCETable {
 587     DeviceState parent;
 588     uint32_t liobn;
 589     uint32_t nb_table;
 590     uint64_t bus_offset;
 591     uint32_t page_shift;
 592     uint64_t *table;
 593     uint32_t mig_nb_table;
 594     uint64_t *mig_table;
 595     bool bypass;
 596     bool need_vfio;
 597     int fd;
 598     MemoryRegion root, iommu;
 599     struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
 600     QLIST_ENTRY(sPAPRTCETable) list;
 601 };
 602
 603 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
 604
 605 struct sPAPREventLogEntry {
 606     int log_type;
 607     void *data;
 608     QTAILQ_ENTRY(sPAPREventLogEntry) next;
 609 };
 610
 611 void spapr_events_init(sPAPRMachineState *sm);
 612 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
 613 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
 614                                  target_ulong addr, target_ulong size,
 615                                  sPAPROptionVector *ov5_updates);
 616 void close_htab_fd(sPAPRMachineState *spapr);
 617 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr);
 618 void spapr_free_hpt(sPAPRMachineState *spapr);
 619 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
 620 void spapr_tce_table_enable(sPAPRTCETable *tcet,
 621                             uint32_t page_shift, uint64_t bus_offset,
 622                             uint32_t nb_table);
 623 void spapr_tce_table_disable(sPAPRTCETable *tcet);
 624 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
 625
 626 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
 627 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 628                  uint32_t liobn, uint64_t window, uint32_t size);
 629 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 630                       sPAPRTCETable *tcet);
 631 void spapr_pci_switch_vga(bool big_endian);
 632 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
 633 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
 634 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
 635                                        uint32_t count);
 636 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
 637                                           uint32_t count);
 638 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
 639                                             uint32_t count, uint32_t index);
 640 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
 641                                                uint32_t count, uint32_t index);
 642 void spapr_cpu_parse_features(sPAPRMachineState *spapr);
 643 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
 644                                     sPAPRMachineState *spapr);
 645
 646 /* CPU and LMB DRC release callbacks. */
 647 void spapr_core_release(DeviceState *dev);
 648 void spapr_lmb_release(DeviceState *dev);
 649
 650 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
 651 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
 652
 653 #define TYPE_SPAPR_RNG "spapr-rng"
 654
 655 int spapr_rng_populate_dt(void *fdt);
 656
 657 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
 658
 659 /*
 660  * This defines the maximum number of DIMM slots we can have for sPAPR
 661  * guest. This is not defined by sPAPR but we are defining it to 32 slots
 662  * based on default number of slots provided by PowerPC kernel.
 663  */
 664 #define SPAPR_MAX_RAM_SLOTS     32
 665
 666 /* 1GB alignment for hotplug memory region */
 667 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
 668
 669 /*
 670  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
 671  * property under ibm,dynamic-reconfiguration-memory node.
 672  */
 673 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
 674
 675 /*
 676  * Defines for flag value in ibm,dynamic-memory property under
 677  * ibm,dynamic-reconfiguration-memory node.
 678  */
 679 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
 680 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
 681 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
 682
 683 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
 684
 685 #endif /* HW_SPAPR_H */