include/hw/ppc/spapr.h

   1 #ifndef HW_SPAPR_H
   2 #define HW_SPAPR_H
   3
   4 #include "sysemu/dma.h"
   5 #include "hw/boards.h"
   6 #include "hw/ppc/xics.h"
   7 #include "hw/ppc/spapr_drc.h"
   8 #include "hw/mem/pc-dimm.h"
   9 #include "hw/ppc/spapr_ovec.h"
  10
  11 struct VIOsPAPRBus;
  12 struct sPAPRPHBState;
  13 struct sPAPRNVRAM;
  14 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
  15 typedef struct sPAPREventSource sPAPREventSource;
  16 typedef struct sPAPRPendingHPT sPAPRPendingHPT;
  17
  18 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  19 #define SPAPR_ENTRY_POINT       0x100
  20
  21 #define SPAPR_TIMEBASE_FREQ     512000000ULL
  22
  23 #define TYPE_SPAPR_RTC "spapr-rtc"
  24
  25 #define SPAPR_RTC(obj)                                  \
  26     OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
  27
  28 typedef struct sPAPRRTCState sPAPRRTCState;
  29 struct sPAPRRTCState {
  30     /*< private >*/
  31     DeviceState parent_obj;
  32     int64_t ns_offset;
  33 };
  34
  35 typedef struct sPAPRDIMMState sPAPRDIMMState;
  36 typedef struct sPAPRMachineClass sPAPRMachineClass;
  37
  38 #define TYPE_SPAPR_MACHINE      "spapr-machine"
  39 #define SPAPR_MACHINE(obj) \
  40     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
  41 #define SPAPR_MACHINE_GET_CLASS(obj) \
  42     OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
  43 #define SPAPR_MACHINE_CLASS(klass) \
  44     OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
  45
  46 typedef enum {
  47     SPAPR_RESIZE_HPT_DEFAULT = 0,
  48     SPAPR_RESIZE_HPT_DISABLED,
  49     SPAPR_RESIZE_HPT_ENABLED,
  50     SPAPR_RESIZE_HPT_REQUIRED,
  51 } sPAPRResizeHPT;
  52
  53 /**
  54  * Capabilities
  55  */
  56
  57 /* Hardware Transactional Memory */
  58 #define SPAPR_CAP_HTM                   0x00
  59 /* Vector Scalar Extensions */
  60 #define SPAPR_CAP_VSX                   0x01
  61 /* Decimal Floating Point */
  62 #define SPAPR_CAP_DFP                   0x02
  63 /* Cache Flush on Privilege Change */
  64 #define SPAPR_CAP_CFPC                  0x03
  65 /* Speculation Barrier Bounds Checking */
  66 #define SPAPR_CAP_SBBC                  0x04
  67 /* Indirect Branch Serialisation */
  68 #define SPAPR_CAP_IBS                   0x05
  69 /* Num Caps */
  70 #define SPAPR_CAP_NUM                   (SPAPR_CAP_IBS + 1)
  71
  72 /*
  73  * Capability Values
  74  */
  75 /* Bool Caps */
  76 #define SPAPR_CAP_OFF                   0x00
  77 #define SPAPR_CAP_ON                    0x01
  78 /* Custom Caps */
  79 #define SPAPR_CAP_BROKEN                0x00
  80 #define SPAPR_CAP_WORKAROUND            0x01
  81 #define SPAPR_CAP_FIXED                 0x02
  82 #define SPAPR_CAP_FIXED_IBS             0x02
  83 #define SPAPR_CAP_FIXED_CCD             0x03
  84
  85 typedef struct sPAPRCapabilities sPAPRCapabilities;
  86 struct sPAPRCapabilities {
  87     uint8_t caps[SPAPR_CAP_NUM];
  88 };
  89
  90 /**
  91  * sPAPRMachineClass:
  92  */
  93 struct sPAPRMachineClass {
  94     /*< private >*/
  95     MachineClass parent_class;
  96
  97     /*< public >*/
  98     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
  99     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
 100     bool pre_2_10_has_unused_icps;
 101     void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
 102                           uint64_t *buid, hwaddr *pio,
 103                           hwaddr *mmio32, hwaddr *mmio64,
 104                           unsigned n_dma, uint32_t *liobns, Error **errp);
 105     sPAPRResizeHPT resize_hpt_default;
 106     sPAPRCapabilities default_caps;
 107 };
 108
 109 /**
 110  * sPAPRMachineState:
 111  */
 112 struct sPAPRMachineState {
 113     /*< private >*/
 114     MachineState parent_obj;
 115
 116     struct VIOsPAPRBus *vio_bus;
 117     QLIST_HEAD(, sPAPRPHBState) phbs;
 118     struct sPAPRNVRAM *nvram;
 119     ICSState *ics;
 120     sPAPRRTCState rtc;
 121
 122     sPAPRResizeHPT resize_hpt;
 123     void *htab;
 124     uint32_t htab_shift;
 125     uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
 126     sPAPRPendingHPT *pending_hpt; /* in-progress resize */
 127
 128     hwaddr rma_size;
 129     int vrma_adjust;
 130     ssize_t rtas_size;
 131     void *rtas_blob;
 132     long kernel_size;
 133     bool kernel_le;
 134     uint32_t initrd_base;
 135     long initrd_size;
 136     uint64_t rtc_offset; /* Now used only during incoming migration */
 137     struct PPCTimebase tb;
 138     bool has_graphics;
 139     uint32_t vsmt;       /* Virtual SMT mode (KVM's "core stride") */
 140
 141     Notifier epow_notifier;
 142     QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
 143     bool use_hotplug_event_source;
 144     sPAPREventSource *event_sources;
 145
 146     /* ibm,client-architecture-support option negotiation */
 147     bool cas_reboot;
 148     bool cas_legacy_guest_workaround;
 149     sPAPROptionVector *ov5;         /* QEMU-supported option vectors */
 150     sPAPROptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
 151     uint32_t max_compat_pvr;
 152
 153     /* Migration state */
 154     int htab_save_index;
 155     bool htab_first_pass;
 156     int htab_fd;
 157
 158     /* Pending DIMM unplug cache. It is populated when a LMB
 159      * unplug starts. It can be regenerated if a migration
 160      * occurs during the unplug process. */
 161     QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs;
 162
 163     /*< public >*/
 164     char *kvm_type;
 165
 166     const char *icp_type;
 167
 168     bool cmd_line_caps[SPAPR_CAP_NUM];
 169     sPAPRCapabilities def, eff, mig;
 170 };
 171
 172 #define H_SUCCESS         0
 173 #define H_BUSY            1        /* Hardware busy -- retry later */
 174 #define H_CLOSED          2        /* Resource closed */
 175 #define H_NOT_AVAILABLE   3
 176 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
 177 #define H_PARTIAL         5
 178 #define H_IN_PROGRESS     14       /* Kind of like busy */
 179 #define H_PAGE_REGISTERED 15
 180 #define H_PARTIAL_STORE   16
 181 #define H_PENDING         17       /* returned from H_POLL_PENDING */
 182 #define H_CONTINUE        18       /* Returned from H_Join on success */
 183 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
 184 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
 185                                                  is a good time to retry */
 186 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
 187                                                  is a good time to retry */
 188 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
 189                                                  is a good time to retry */
 190 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
 191                                                  is a good time to retry */
 192 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
 193                                                  is a good time to retry */
 194 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
 195                                                  is a good time to retry */
 196 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
 197 #define H_HARDWARE        -1       /* Hardware error */
 198 #define H_FUNCTION        -2       /* Function not supported */
 199 #define H_PRIVILEGE       -3       /* Caller not privileged */
 200 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
 201 #define H_BAD_MODE        -5       /* Illegal msr value */
 202 #define H_PTEG_FULL       -6       /* PTEG is full */
 203 #define H_NOT_FOUND       -7       /* PTE was not found" */
 204 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
 205 #define H_NO_MEM          -9
 206 #define H_AUTHORITY       -10
 207 #define H_PERMISSION      -11
 208 #define H_DROPPED         -12
 209 #define H_SOURCE_PARM     -13
 210 #define H_DEST_PARM       -14
 211 #define H_REMOTE_PARM     -15
 212 #define H_RESOURCE        -16
 213 #define H_ADAPTER_PARM    -17
 214 #define H_RH_PARM         -18
 215 #define H_RCQ_PARM        -19
 216 #define H_SCQ_PARM        -20
 217 #define H_EQ_PARM         -21
 218 #define H_RT_PARM         -22
 219 #define H_ST_PARM         -23
 220 #define H_SIGT_PARM       -24
 221 #define H_TOKEN_PARM      -25
 222 #define H_MLENGTH_PARM    -27
 223 #define H_MEM_PARM        -28
 224 #define H_MEM_ACCESS_PARM -29
 225 #define H_ATTR_PARM       -30
 226 #define H_PORT_PARM       -31
 227 #define H_MCG_PARM        -32
 228 #define H_VL_PARM         -33
 229 #define H_TSIZE_PARM      -34
 230 #define H_TRACE_PARM      -35
 231
 232 #define H_MASK_PARM       -37
 233 #define H_MCG_FULL        -38
 234 #define H_ALIAS_EXIST     -39
 235 #define H_P_COUNTER       -40
 236 #define H_TABLE_FULL      -41
 237 #define H_ALT_TABLE       -42
 238 #define H_MR_CONDITION    -43
 239 #define H_NOT_ENOUGH_RESOURCES -44
 240 #define H_R_STATE         -45
 241 #define H_RESCINDEND      -46
 242 #define H_P2              -55
 243 #define H_P3              -56
 244 #define H_P4              -57
 245 #define H_P5              -58
 246 #define H_P6              -59
 247 #define H_P7              -60
 248 #define H_P8              -61
 249 #define H_P9              -62
 250 #define H_UNSUPPORTED_FLAG -256
 251 #define H_MULTI_THREADS_ACTIVE -9005
 252
 253
 254 /* Long Busy is a condition that can be returned by the firmware
 255  * when a call cannot be completed now, but the identical call
 256  * should be retried later.  This prevents calls blocking in the
 257  * firmware for long periods of time.  Annoyingly the firmware can return
 258  * a range of return codes, hinting at how long we should wait before
 259  * retrying.  If you don't care for the hint, the macro below is a good
 260  * way to check for the long_busy return codes
 261  */
 262 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 263                             && (x <= H_LONG_BUSY_END_RANGE))
 264
 265 /* Flags */
 266 #define H_LARGE_PAGE      (1ULL<<(63-16))
 267 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 268 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 269 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 270 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 271 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 272 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 273 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 274 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 275 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 276 #define H_ANDCOND         (1ULL<<(63-33))
 277 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 278 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 279 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 280 #define H_COPY_PAGE       (1ULL<<(63-49))
 281 #define H_N               (1ULL<<(63-61))
 282 #define H_PP1             (1ULL<<(63-62))
 283 #define H_PP2             (1ULL<<(63-63))
 284
 285 /* Values for 2nd argument to H_SET_MODE */
 286 #define H_SET_MODE_RESOURCE_SET_CIABR           1
 287 #define H_SET_MODE_RESOURCE_SET_DAWR            2
 288 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 289 #define H_SET_MODE_RESOURCE_LE                  4
 290
 291 /* Flags for H_SET_MODE_RESOURCE_LE */
 292 #define H_SET_MODE_ENDIAN_BIG    0
 293 #define H_SET_MODE_ENDIAN_LITTLE 1
 294
 295 /* VASI States */
 296 #define H_VASI_INVALID    0
 297 #define H_VASI_ENABLED    1
 298 #define H_VASI_ABORTED    2
 299 #define H_VASI_SUSPENDING 3
 300 #define H_VASI_SUSPENDED  4
 301 #define H_VASI_RESUMED    5
 302 #define H_VASI_COMPLETED  6
 303
 304 /* DABRX flags */
 305 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 306 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 307 #define H_DABRX_USER       (1ULL<<(63-63))
 308
 309 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
 310 #define H_CPU_CHAR_SPEC_BAR_ORI31               PPC_BIT(0)
 311 #define H_CPU_CHAR_BCCTRL_SERIALISED            PPC_BIT(1)
 312 #define H_CPU_CHAR_L1D_FLUSH_ORI30              PPC_BIT(2)
 313 #define H_CPU_CHAR_L1D_FLUSH_TRIG2              PPC_BIT(3)
 314 #define H_CPU_CHAR_L1D_THREAD_PRIV              PPC_BIT(4)
 315 #define H_CPU_CHAR_HON_BRANCH_HINTS             PPC_BIT(5)
 316 #define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
 317 #define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
 318 #define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
 319 #define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
 320 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
 321
 322 /* Each control block has to be on a 4K boundary */
 323 #define H_CB_ALIGNMENT     4096
 324
 325 /* pSeries hypervisor opcodes */
 326 #define H_REMOVE                0x04
 327 #define H_ENTER                 0x08
 328 #define H_READ                  0x0c
 329 #define H_CLEAR_MOD             0x10
 330 #define H_CLEAR_REF             0x14
 331 #define H_PROTECT               0x18
 332 #define H_GET_TCE               0x1c
 333 #define H_PUT_TCE               0x20
 334 #define H_SET_SPRG0             0x24
 335 #define H_SET_DABR              0x28
 336 #define H_PAGE_INIT             0x2c
 337 #define H_SET_ASR               0x30
 338 #define H_ASR_ON                0x34
 339 #define H_ASR_OFF               0x38
 340 #define H_LOGICAL_CI_LOAD       0x3c
 341 #define H_LOGICAL_CI_STORE      0x40
 342 #define H_LOGICAL_CACHE_LOAD    0x44
 343 #define H_LOGICAL_CACHE_STORE   0x48
 344 #define H_LOGICAL_ICBI          0x4c
 345 #define H_LOGICAL_DCBF          0x50
 346 #define H_GET_TERM_CHAR         0x54
 347 #define H_PUT_TERM_CHAR         0x58
 348 #define H_REAL_TO_LOGICAL       0x5c
 349 #define H_HYPERVISOR_DATA       0x60
 350 #define H_EOI                   0x64
 351 #define H_CPPR                  0x68
 352 #define H_IPI                   0x6c
 353 #define H_IPOLL                 0x70
 354 #define H_XIRR                  0x74
 355 #define H_PERFMON               0x7c
 356 #define H_MIGRATE_DMA           0x78
 357 #define H_REGISTER_VPA          0xDC
 358 #define H_CEDE                  0xE0
 359 #define H_CONFER                0xE4
 360 #define H_PROD                  0xE8
 361 #define H_GET_PPP               0xEC
 362 #define H_SET_PPP               0xF0
 363 #define H_PURR                  0xF4
 364 #define H_PIC                   0xF8
 365 #define H_REG_CRQ               0xFC
 366 #define H_FREE_CRQ              0x100
 367 #define H_VIO_SIGNAL            0x104
 368 #define H_SEND_CRQ              0x108
 369 #define H_COPY_RDMA             0x110
 370 #define H_REGISTER_LOGICAL_LAN  0x114
 371 #define H_FREE_LOGICAL_LAN      0x118
 372 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 373 #define H_SEND_LOGICAL_LAN      0x120
 374 #define H_BULK_REMOVE           0x124
 375 #define H_MULTICAST_CTRL        0x130
 376 #define H_SET_XDABR             0x134
 377 #define H_STUFF_TCE             0x138
 378 #define H_PUT_TCE_INDIRECT      0x13C
 379 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 380 #define H_VTERM_PARTNER_INFO    0x150
 381 #define H_REGISTER_VTERM        0x154
 382 #define H_FREE_VTERM            0x158
 383 #define H_RESET_EVENTS          0x15C
 384 #define H_ALLOC_RESOURCE        0x160
 385 #define H_FREE_RESOURCE         0x164
 386 #define H_MODIFY_QP             0x168
 387 #define H_QUERY_QP              0x16C
 388 #define H_REREGISTER_PMR        0x170
 389 #define H_REGISTER_SMR          0x174
 390 #define H_QUERY_MR              0x178
 391 #define H_QUERY_MW              0x17C
 392 #define H_QUERY_HCA             0x180
 393 #define H_QUERY_PORT            0x184
 394 #define H_MODIFY_PORT           0x188
 395 #define H_DEFINE_AQP1           0x18C
 396 #define H_GET_TRACE_BUFFER      0x190
 397 #define H_DEFINE_AQP0           0x194
 398 #define H_RESIZE_MR             0x198
 399 #define H_ATTACH_MCQP           0x19C
 400 #define H_DETACH_MCQP           0x1A0
 401 #define H_CREATE_RPT            0x1A4
 402 #define H_REMOVE_RPT            0x1A8
 403 #define H_REGISTER_RPAGES       0x1AC
 404 #define H_DISABLE_AND_GETC      0x1B0
 405 #define H_ERROR_DATA            0x1B4
 406 #define H_GET_HCA_INFO          0x1B8
 407 #define H_GET_PERF_COUNT        0x1BC
 408 #define H_MANAGE_TRACE          0x1C0
 409 #define H_GET_CPU_CHARACTERISTICS 0x1C8
 410 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 411 #define H_QUERY_INT_STATE       0x1E4
 412 #define H_POLL_PENDING          0x1D8
 413 #define H_ILLAN_ATTRIBUTES      0x244
 414 #define H_MODIFY_HEA_QP         0x250
 415 #define H_QUERY_HEA_QP          0x254
 416 #define H_QUERY_HEA             0x258
 417 #define H_QUERY_HEA_PORT        0x25C
 418 #define H_MODIFY_HEA_PORT       0x260
 419 #define H_REG_BCMC              0x264
 420 #define H_DEREG_BCMC            0x268
 421 #define H_REGISTER_HEA_RPAGES   0x26C
 422 #define H_DISABLE_AND_GET_HEA   0x270
 423 #define H_GET_HEA_INFO          0x274
 424 #define H_ALLOC_HEA_RESOURCE    0x278
 425 #define H_ADD_CONN              0x284
 426 #define H_DEL_CONN              0x288
 427 #define H_JOIN                  0x298
 428 #define H_VASI_STATE            0x2A4
 429 #define H_ENABLE_CRQ            0x2B0
 430 #define H_GET_EM_PARMS          0x2B8
 431 #define H_SET_MPP               0x2D0
 432 #define H_GET_MPP               0x2D4
 433 #define H_XIRR_X                0x2FC
 434 #define H_RANDOM                0x300
 435 #define H_SET_MODE              0x31C
 436 #define H_RESIZE_HPT_PREPARE    0x36C
 437 #define H_RESIZE_HPT_COMMIT     0x370
 438 #define H_CLEAN_SLB             0x374
 439 #define H_INVALIDATE_PID        0x378
 440 #define H_REGISTER_PROC_TBL     0x37C
 441 #define H_SIGNAL_SYS_RESET      0x380
 442 #define MAX_HCALL_OPCODE        H_SIGNAL_SYS_RESET
 443
 444 /* The hcalls above are standardized in PAPR and implemented by pHyp
 445  * as well.
 446  *
 447  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 448  * We put those into the 0xf000-0xfffc range which is reserved by PAPR
 449  * for "platform-specific" hcalls.
 450  */
 451 #define KVMPPC_HCALL_BASE       0xf000
 452 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 453 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 454 /* Client Architecture support */
 455 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 456 #define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
 457
 458 typedef struct sPAPRDeviceTreeUpdateHeader {
 459     uint32_t version_id;
 460 } sPAPRDeviceTreeUpdateHeader;
 461
 462 #define hcall_dprintf(fmt, ...) \
 463     do { \
 464         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
 465     } while (0)
 466
 467 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 468                                        target_ulong opcode,
 469                                        target_ulong *args);
 470
 471 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 472 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 473                              target_ulong *args);
 474
 475 /* ibm,set-eeh-option */
 476 #define RTAS_EEH_DISABLE                 0
 477 #define RTAS_EEH_ENABLE                  1
 478 #define RTAS_EEH_THAW_IO                 2
 479 #define RTAS_EEH_THAW_DMA                3
 480
 481 /* ibm,get-config-addr-info2 */
 482 #define RTAS_GET_PE_ADDR                 0
 483 #define RTAS_GET_PE_MODE                 1
 484 #define RTAS_PE_MODE_NONE                0
 485 #define RTAS_PE_MODE_NOT_SHARED          1
 486 #define RTAS_PE_MODE_SHARED              2
 487
 488 /* ibm,read-slot-reset-state2 */
 489 #define RTAS_EEH_PE_STATE_NORMAL         0
 490 #define RTAS_EEH_PE_STATE_RESET          1
 491 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
 492 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
 493 #define RTAS_EEH_PE_STATE_UNAVAIL        5
 494 #define RTAS_EEH_NOT_SUPPORT             0
 495 #define RTAS_EEH_SUPPORT                 1
 496 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
 497 #define RTAS_EEH_PE_RECOVER_INFO         0
 498
 499 /* ibm,set-slot-reset */
 500 #define RTAS_SLOT_RESET_DEACTIVATE       0
 501 #define RTAS_SLOT_RESET_HOT              1
 502 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
 503
 504 /* ibm,slot-error-detail */
 505 #define RTAS_SLOT_TEMP_ERR_LOG           1
 506 #define RTAS_SLOT_PERM_ERR_LOG           2
 507
 508 /* RTAS return codes */
 509 #define RTAS_OUT_SUCCESS                        0
 510 #define RTAS_OUT_NO_ERRORS_FOUND                1
 511 #define RTAS_OUT_HW_ERROR                       -1
 512 #define RTAS_OUT_BUSY                           -2
 513 #define RTAS_OUT_PARAM_ERROR                    -3
 514 #define RTAS_OUT_NOT_SUPPORTED                  -3
 515 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
 516 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
 517 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
 518
 519 /* DDW pagesize mask values from ibm,query-pe-dma-window */
 520 #define RTAS_DDW_PGSIZE_4K       0x01
 521 #define RTAS_DDW_PGSIZE_64K      0x02
 522 #define RTAS_DDW_PGSIZE_16M      0x04
 523 #define RTAS_DDW_PGSIZE_32M      0x08
 524 #define RTAS_DDW_PGSIZE_64M      0x10
 525 #define RTAS_DDW_PGSIZE_128M     0x20
 526 #define RTAS_DDW_PGSIZE_256M     0x40
 527 #define RTAS_DDW_PGSIZE_16G      0x80
 528
 529 /* RTAS tokens */
 530 #define RTAS_TOKEN_BASE      0x2000
 531
 532 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 533 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 534 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 535 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 536 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 537 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 538 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 539 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 540 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 541 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 542 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 543 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 544 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 545 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 546 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 547 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 548 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 549 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 550 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 551 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 552 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 553 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 554 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 555 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 556 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 557 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 558 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 559 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 560 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 561 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 562 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 563 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 564 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
 565 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
 566 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
 567 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
 568 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
 569 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
 570 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
 571 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
 572 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
 573 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
 574
 575 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2A)
 576
 577 /* RTAS ibm,get-system-parameter token values */
 578 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 579 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 580 #define RTAS_SYSPARM_UUID                        48
 581
 582 /* RTAS indicator/sensor types
 583  *
 584  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
 585  *
 586  * NOTE: currently only DR-related sensors are implemented here
 587  */
 588 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
 589 #define RTAS_SENSOR_TYPE_DR                     9002
 590 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
 591 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
 592
 593 /* Possible values for the platform-processor-diagnostics-run-mode parameter
 594  * of the RTAS ibm,get-system-parameter call.
 595  */
 596 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
 597 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 598 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 599 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 600
 601 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 602 {
 603     return addr & ~0xF000000000000000ULL;
 604 }
 605
 606 static inline uint32_t rtas_ld(target_ulong phys, int n)
 607 {
 608     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 609 }
 610
 611 static inline uint64_t rtas_ldq(target_ulong phys, int n)
 612 {
 613     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
 614 }
 615
 616 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 617 {
 618     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 619 }
 620
 621 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 622                               uint32_t token,
 623                               uint32_t nargs, target_ulong args,
 624                               uint32_t nret, target_ulong rets);
 625 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 626 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
 627                              uint32_t token, uint32_t nargs, target_ulong args,
 628                              uint32_t nret, target_ulong rets);
 629 void spapr_dt_rtas_tokens(void *fdt, int rtas);
 630 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
 631
 632 #define SPAPR_TCE_PAGE_SHIFT   12
 633 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 634 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 635
 636 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 637 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
 638 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
 639     (0x80000000 | ((phb_index) << 8) | (window_num))
 640 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
 641 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
 642
 643 #define RTAS_ERROR_LOG_MAX      2048
 644
 645 #define RTAS_EVENT_SCAN_RATE    1
 646
 647 /* This helper should be used to encode interrupt specifiers when the related
 648  * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
 649  * VIO devices, RTAS event sources and PHBs).
 650  */
 651 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi)
 652 {
 653     intspec[0] = cpu_to_be32(irq);
 654     intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
 655 }
 656
 657 typedef struct sPAPRTCETable sPAPRTCETable;
 658
 659 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 660 #define SPAPR_TCE_TABLE(obj) \
 661     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
 662
 663 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
 664 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
 665         OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
 666
 667 struct sPAPRTCETable {
 668     DeviceState parent;
 669     uint32_t liobn;
 670     uint32_t nb_table;
 671     uint64_t bus_offset;
 672     uint32_t page_shift;
 673     uint64_t *table;
 674     uint32_t mig_nb_table;
 675     uint64_t *mig_table;
 676     bool bypass;
 677     bool need_vfio;
 678     int fd;
 679     MemoryRegion root;
 680     IOMMUMemoryRegion iommu;
 681     struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
 682     QLIST_ENTRY(sPAPRTCETable) list;
 683 };
 684
 685 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
 686
 687 struct sPAPREventLogEntry {
 688     uint32_t summary;
 689     uint32_t extended_length;
 690     void *extended_log;
 691     QTAILQ_ENTRY(sPAPREventLogEntry) next;
 692 };
 693
 694 void spapr_events_init(sPAPRMachineState *sm);
 695 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
 696 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
 697                                  target_ulong addr, target_ulong size,
 698                                  sPAPROptionVector *ov5_updates);
 699 void close_htab_fd(sPAPRMachineState *spapr);
 700 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr);
 701 void spapr_free_hpt(sPAPRMachineState *spapr);
 702 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
 703 void spapr_tce_table_enable(sPAPRTCETable *tcet,
 704                             uint32_t page_shift, uint64_t bus_offset,
 705                             uint32_t nb_table);
 706 void spapr_tce_table_disable(sPAPRTCETable *tcet);
 707 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
 708
 709 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
 710 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 711                  uint32_t liobn, uint64_t window, uint32_t size);
 712 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 713                       sPAPRTCETable *tcet);
 714 void spapr_pci_switch_vga(bool big_endian);
 715 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
 716 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
 717 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
 718                                        uint32_t count);
 719 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
 720                                           uint32_t count);
 721 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
 722                                             uint32_t count, uint32_t index);
 723 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
 724                                                uint32_t count, uint32_t index);
 725 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
 726 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
 727                           Error **errp);
 728 void spapr_clear_pending_events(sPAPRMachineState *spapr);
 729
 730 /* CPU and LMB DRC release callbacks. */
 731 void spapr_core_release(DeviceState *dev);
 732 void spapr_lmb_release(DeviceState *dev);
 733
 734 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
 735 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
 736
 737 #define TYPE_SPAPR_RNG "spapr-rng"
 738
 739 int spapr_rng_populate_dt(void *fdt);
 740
 741 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
 742
 743 /*
 744  * This defines the maximum number of DIMM slots we can have for sPAPR
 745  * guest. This is not defined by sPAPR but we are defining it to 32 slots
 746  * based on default number of slots provided by PowerPC kernel.
 747  */
 748 #define SPAPR_MAX_RAM_SLOTS     32
 749
 750 /* 1GB alignment for device memory region */
 751 #define SPAPR_DEVICE_MEM_ALIGN (1ULL << 30)
 752
 753 /*
 754  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
 755  * property under ibm,dynamic-reconfiguration-memory node.
 756  */
 757 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
 758
 759 /*
 760  * Defines for flag value in ibm,dynamic-memory property under
 761  * ibm,dynamic-reconfiguration-memory node.
 762  */
 763 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
 764 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
 765 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
 766
 767 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
 768
 769 #define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
 770
 771 int spapr_get_vcpu_id(PowerPCCPU *cpu);
 772 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
 773 PowerPCCPU *spapr_find_cpu(int vcpu_id);
 774
 775 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align,
 776                    Error **errp);
 777 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
 778 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
 779 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
 780 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
 781
 782
 783 int spapr_caps_pre_load(void *opaque);
 784 int spapr_caps_pre_save(void *opaque);
 785
 786 /*
 787  * Handling of optional capabilities
 788  */
 789 extern const VMStateDescription vmstate_spapr_cap_htm;
 790 extern const VMStateDescription vmstate_spapr_cap_vsx;
 791 extern const VMStateDescription vmstate_spapr_cap_dfp;
 792 extern const VMStateDescription vmstate_spapr_cap_cfpc;
 793 extern const VMStateDescription vmstate_spapr_cap_sbbc;
 794 extern const VMStateDescription vmstate_spapr_cap_ibs;
 795
 796 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
 797 {
 798     return spapr->eff.caps[cap];
 799 }
 800
 801 void spapr_caps_init(sPAPRMachineState *spapr);
 802 void spapr_caps_apply(sPAPRMachineState *spapr);
 803 void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu);
 804 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp);
 805 int spapr_caps_post_migration(sPAPRMachineState *spapr);
 806
 807 #endif /* HW_SPAPR_H */