include/hw/ppc/spapr.h

   1 #ifndef HW_SPAPR_H
   2 #define HW_SPAPR_H
   3
   4 #include "sysemu/dma.h"
   5 #include "hw/boards.h"
   6 #include "hw/ppc/xics.h"
   7 #include "hw/ppc/spapr_drc.h"
   8 #include "hw/mem/pc-dimm.h"
   9 #include "hw/ppc/spapr_ovec.h"
  10
  11 struct VIOsPAPRBus;
  12 struct sPAPRPHBState;
  13 struct sPAPRNVRAM;
  14 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
  15 typedef struct sPAPREventSource sPAPREventSource;
  16 typedef struct sPAPRPendingHPT sPAPRPendingHPT;
  17
  18 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  19 #define SPAPR_ENTRY_POINT       0x100
  20
  21 #define SPAPR_TIMEBASE_FREQ     512000000ULL
  22
  23 #define TYPE_SPAPR_RTC "spapr-rtc"
  24
  25 #define SPAPR_RTC(obj)                                  \
  26     OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
  27
  28 typedef struct sPAPRRTCState sPAPRRTCState;
  29 struct sPAPRRTCState {
  30     /*< private >*/
  31     DeviceState parent_obj;
  32     int64_t ns_offset;
  33 };
  34
  35 typedef struct sPAPRDIMMState sPAPRDIMMState;
  36 typedef struct sPAPRMachineClass sPAPRMachineClass;
  37
  38 #define TYPE_SPAPR_MACHINE      "spapr-machine"
  39 #define SPAPR_MACHINE(obj) \
  40     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
  41 #define SPAPR_MACHINE_GET_CLASS(obj) \
  42     OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
  43 #define SPAPR_MACHINE_CLASS(klass) \
  44     OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
  45
  46 typedef enum {
  47     SPAPR_RESIZE_HPT_DEFAULT = 0,
  48     SPAPR_RESIZE_HPT_DISABLED,
  49     SPAPR_RESIZE_HPT_ENABLED,
  50     SPAPR_RESIZE_HPT_REQUIRED,
  51 } sPAPRResizeHPT;
  52
  53 /**
  54  * sPAPRMachineClass:
  55  */
  56 struct sPAPRMachineClass {
  57     /*< private >*/
  58     MachineClass parent_class;
  59
  60     /*< public >*/
  61     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
  62     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
  63     bool pre_2_10_has_unused_icps;
  64     void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
  65                           uint64_t *buid, hwaddr *pio,
  66                           hwaddr *mmio32, hwaddr *mmio64,
  67                           unsigned n_dma, uint32_t *liobns, Error **errp);
  68     sPAPRResizeHPT resize_hpt_default;
  69 };
  70
  71 /**
  72  * sPAPRMachineState:
  73  */
  74 struct sPAPRMachineState {
  75     /*< private >*/
  76     MachineState parent_obj;
  77
  78     struct VIOsPAPRBus *vio_bus;
  79     QLIST_HEAD(, sPAPRPHBState) phbs;
  80     struct sPAPRNVRAM *nvram;
  81     ICSState *ics;
  82     sPAPRRTCState rtc;
  83
  84     sPAPRResizeHPT resize_hpt;
  85     void *htab;
  86     uint32_t htab_shift;
  87     uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
  88     sPAPRPendingHPT *pending_hpt; /* in-progress resize */
  89
  90     hwaddr rma_size;
  91     int vrma_adjust;
  92     ssize_t rtas_size;
  93     void *rtas_blob;
  94     long kernel_size;
  95     bool kernel_le;
  96     uint32_t initrd_base;
  97     long initrd_size;
  98     uint64_t rtc_offset; /* Now used only during incoming migration */
  99     struct PPCTimebase tb;
 100     bool has_graphics;
 101     uint32_t vsmt;       /* Virtual SMT mode (KVM's "core stride") */
 102
 103     Notifier epow_notifier;
 104     QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
 105     bool use_hotplug_event_source;
 106     sPAPREventSource *event_sources;
 107
 108     /* ibm,client-architecture-support option negotiation */
 109     bool cas_reboot;
 110     bool cas_legacy_guest_workaround;
 111     sPAPROptionVector *ov5;         /* QEMU-supported option vectors */
 112     sPAPROptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
 113     uint32_t max_compat_pvr;
 114
 115     /* Migration state */
 116     int htab_save_index;
 117     bool htab_first_pass;
 118     int htab_fd;
 119
 120     /* Pending DIMM unplug cache. It is populated when a LMB
 121      * unplug starts. It can be regenerated if a migration
 122      * occurs during the unplug process. */
 123     QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs;
 124
 125     /*< public >*/
 126     char *kvm_type;
 127     MemoryHotplugState hotplug_memory;
 128
 129     const char *icp_type;
 130 };
 131
 132 #define H_SUCCESS         0
 133 #define H_BUSY            1        /* Hardware busy -- retry later */
 134 #define H_CLOSED          2        /* Resource closed */
 135 #define H_NOT_AVAILABLE   3
 136 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
 137 #define H_PARTIAL         5
 138 #define H_IN_PROGRESS     14       /* Kind of like busy */
 139 #define H_PAGE_REGISTERED 15
 140 #define H_PARTIAL_STORE   16
 141 #define H_PENDING         17       /* returned from H_POLL_PENDING */
 142 #define H_CONTINUE        18       /* Returned from H_Join on success */
 143 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
 144 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
 145                                                  is a good time to retry */
 146 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
 147                                                  is a good time to retry */
 148 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
 149                                                  is a good time to retry */
 150 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
 151                                                  is a good time to retry */
 152 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
 153                                                  is a good time to retry */
 154 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
 155                                                  is a good time to retry */
 156 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
 157 #define H_HARDWARE        -1       /* Hardware error */
 158 #define H_FUNCTION        -2       /* Function not supported */
 159 #define H_PRIVILEGE       -3       /* Caller not privileged */
 160 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
 161 #define H_BAD_MODE        -5       /* Illegal msr value */
 162 #define H_PTEG_FULL       -6       /* PTEG is full */
 163 #define H_NOT_FOUND       -7       /* PTE was not found" */
 164 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
 165 #define H_NO_MEM          -9
 166 #define H_AUTHORITY       -10
 167 #define H_PERMISSION      -11
 168 #define H_DROPPED         -12
 169 #define H_SOURCE_PARM     -13
 170 #define H_DEST_PARM       -14
 171 #define H_REMOTE_PARM     -15
 172 #define H_RESOURCE        -16
 173 #define H_ADAPTER_PARM    -17
 174 #define H_RH_PARM         -18
 175 #define H_RCQ_PARM        -19
 176 #define H_SCQ_PARM        -20
 177 #define H_EQ_PARM         -21
 178 #define H_RT_PARM         -22
 179 #define H_ST_PARM         -23
 180 #define H_SIGT_PARM       -24
 181 #define H_TOKEN_PARM      -25
 182 #define H_MLENGTH_PARM    -27
 183 #define H_MEM_PARM        -28
 184 #define H_MEM_ACCESS_PARM -29
 185 #define H_ATTR_PARM       -30
 186 #define H_PORT_PARM       -31
 187 #define H_MCG_PARM        -32
 188 #define H_VL_PARM         -33
 189 #define H_TSIZE_PARM      -34
 190 #define H_TRACE_PARM      -35
 191
 192 #define H_MASK_PARM       -37
 193 #define H_MCG_FULL        -38
 194 #define H_ALIAS_EXIST     -39
 195 #define H_P_COUNTER       -40
 196 #define H_TABLE_FULL      -41
 197 #define H_ALT_TABLE       -42
 198 #define H_MR_CONDITION    -43
 199 #define H_NOT_ENOUGH_RESOURCES -44
 200 #define H_R_STATE         -45
 201 #define H_RESCINDEND      -46
 202 #define H_P2              -55
 203 #define H_P3              -56
 204 #define H_P4              -57
 205 #define H_P5              -58
 206 #define H_P6              -59
 207 #define H_P7              -60
 208 #define H_P8              -61
 209 #define H_P9              -62
 210 #define H_UNSUPPORTED_FLAG -256
 211 #define H_MULTI_THREADS_ACTIVE -9005
 212
 213
 214 /* Long Busy is a condition that can be returned by the firmware
 215  * when a call cannot be completed now, but the identical call
 216  * should be retried later.  This prevents calls blocking in the
 217  * firmware for long periods of time.  Annoyingly the firmware can return
 218  * a range of return codes, hinting at how long we should wait before
 219  * retrying.  If you don't care for the hint, the macro below is a good
 220  * way to check for the long_busy return codes
 221  */
 222 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 223                             && (x <= H_LONG_BUSY_END_RANGE))
 224
 225 /* Flags */
 226 #define H_LARGE_PAGE      (1ULL<<(63-16))
 227 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 228 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 229 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 230 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 231 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 232 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 233 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 234 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 235 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 236 #define H_ANDCOND         (1ULL<<(63-33))
 237 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 238 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 239 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 240 #define H_COPY_PAGE       (1ULL<<(63-49))
 241 #define H_N               (1ULL<<(63-61))
 242 #define H_PP1             (1ULL<<(63-62))
 243 #define H_PP2             (1ULL<<(63-63))
 244
 245 /* Values for 2nd argument to H_SET_MODE */
 246 #define H_SET_MODE_RESOURCE_SET_CIABR           1
 247 #define H_SET_MODE_RESOURCE_SET_DAWR            2
 248 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 249 #define H_SET_MODE_RESOURCE_LE                  4
 250
 251 /* Flags for H_SET_MODE_RESOURCE_LE */
 252 #define H_SET_MODE_ENDIAN_BIG    0
 253 #define H_SET_MODE_ENDIAN_LITTLE 1
 254
 255 /* VASI States */
 256 #define H_VASI_INVALID    0
 257 #define H_VASI_ENABLED    1
 258 #define H_VASI_ABORTED    2
 259 #define H_VASI_SUSPENDING 3
 260 #define H_VASI_SUSPENDED  4
 261 #define H_VASI_RESUMED    5
 262 #define H_VASI_COMPLETED  6
 263
 264 /* DABRX flags */
 265 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 266 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 267 #define H_DABRX_USER       (1ULL<<(63-63))
 268
 269 /* Each control block has to be on a 4K boundary */
 270 #define H_CB_ALIGNMENT     4096
 271
 272 /* pSeries hypervisor opcodes */
 273 #define H_REMOVE                0x04
 274 #define H_ENTER                 0x08
 275 #define H_READ                  0x0c
 276 #define H_CLEAR_MOD             0x10
 277 #define H_CLEAR_REF             0x14
 278 #define H_PROTECT               0x18
 279 #define H_GET_TCE               0x1c
 280 #define H_PUT_TCE               0x20
 281 #define H_SET_SPRG0             0x24
 282 #define H_SET_DABR              0x28
 283 #define H_PAGE_INIT             0x2c
 284 #define H_SET_ASR               0x30
 285 #define H_ASR_ON                0x34
 286 #define H_ASR_OFF               0x38
 287 #define H_LOGICAL_CI_LOAD       0x3c
 288 #define H_LOGICAL_CI_STORE      0x40
 289 #define H_LOGICAL_CACHE_LOAD    0x44
 290 #define H_LOGICAL_CACHE_STORE   0x48
 291 #define H_LOGICAL_ICBI          0x4c
 292 #define H_LOGICAL_DCBF          0x50
 293 #define H_GET_TERM_CHAR         0x54
 294 #define H_PUT_TERM_CHAR         0x58
 295 #define H_REAL_TO_LOGICAL       0x5c
 296 #define H_HYPERVISOR_DATA       0x60
 297 #define H_EOI                   0x64
 298 #define H_CPPR                  0x68
 299 #define H_IPI                   0x6c
 300 #define H_IPOLL                 0x70
 301 #define H_XIRR                  0x74
 302 #define H_PERFMON               0x7c
 303 #define H_MIGRATE_DMA           0x78
 304 #define H_REGISTER_VPA          0xDC
 305 #define H_CEDE                  0xE0
 306 #define H_CONFER                0xE4
 307 #define H_PROD                  0xE8
 308 #define H_GET_PPP               0xEC
 309 #define H_SET_PPP               0xF0
 310 #define H_PURR                  0xF4
 311 #define H_PIC                   0xF8
 312 #define H_REG_CRQ               0xFC
 313 #define H_FREE_CRQ              0x100
 314 #define H_VIO_SIGNAL            0x104
 315 #define H_SEND_CRQ              0x108
 316 #define H_COPY_RDMA             0x110
 317 #define H_REGISTER_LOGICAL_LAN  0x114
 318 #define H_FREE_LOGICAL_LAN      0x118
 319 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 320 #define H_SEND_LOGICAL_LAN      0x120
 321 #define H_BULK_REMOVE           0x124
 322 #define H_MULTICAST_CTRL        0x130
 323 #define H_SET_XDABR             0x134
 324 #define H_STUFF_TCE             0x138
 325 #define H_PUT_TCE_INDIRECT      0x13C
 326 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 327 #define H_VTERM_PARTNER_INFO    0x150
 328 #define H_REGISTER_VTERM        0x154
 329 #define H_FREE_VTERM            0x158
 330 #define H_RESET_EVENTS          0x15C
 331 #define H_ALLOC_RESOURCE        0x160
 332 #define H_FREE_RESOURCE         0x164
 333 #define H_MODIFY_QP             0x168
 334 #define H_QUERY_QP              0x16C
 335 #define H_REREGISTER_PMR        0x170
 336 #define H_REGISTER_SMR          0x174
 337 #define H_QUERY_MR              0x178
 338 #define H_QUERY_MW              0x17C
 339 #define H_QUERY_HCA             0x180
 340 #define H_QUERY_PORT            0x184
 341 #define H_MODIFY_PORT           0x188
 342 #define H_DEFINE_AQP1           0x18C
 343 #define H_GET_TRACE_BUFFER      0x190
 344 #define H_DEFINE_AQP0           0x194
 345 #define H_RESIZE_MR             0x198
 346 #define H_ATTACH_MCQP           0x19C
 347 #define H_DETACH_MCQP           0x1A0
 348 #define H_CREATE_RPT            0x1A4
 349 #define H_REMOVE_RPT            0x1A8
 350 #define H_REGISTER_RPAGES       0x1AC
 351 #define H_DISABLE_AND_GETC      0x1B0
 352 #define H_ERROR_DATA            0x1B4
 353 #define H_GET_HCA_INFO          0x1B8
 354 #define H_GET_PERF_COUNT        0x1BC
 355 #define H_MANAGE_TRACE          0x1C0
 356 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 357 #define H_QUERY_INT_STATE       0x1E4
 358 #define H_POLL_PENDING          0x1D8
 359 #define H_ILLAN_ATTRIBUTES      0x244
 360 #define H_MODIFY_HEA_QP         0x250
 361 #define H_QUERY_HEA_QP          0x254
 362 #define H_QUERY_HEA             0x258
 363 #define H_QUERY_HEA_PORT        0x25C
 364 #define H_MODIFY_HEA_PORT       0x260
 365 #define H_REG_BCMC              0x264
 366 #define H_DEREG_BCMC            0x268
 367 #define H_REGISTER_HEA_RPAGES   0x26C
 368 #define H_DISABLE_AND_GET_HEA   0x270
 369 #define H_GET_HEA_INFO          0x274
 370 #define H_ALLOC_HEA_RESOURCE    0x278
 371 #define H_ADD_CONN              0x284
 372 #define H_DEL_CONN              0x288
 373 #define H_JOIN                  0x298
 374 #define H_VASI_STATE            0x2A4
 375 #define H_ENABLE_CRQ            0x2B0
 376 #define H_GET_EM_PARMS          0x2B8
 377 #define H_SET_MPP               0x2D0
 378 #define H_GET_MPP               0x2D4
 379 #define H_XIRR_X                0x2FC
 380 #define H_RANDOM                0x300
 381 #define H_SET_MODE              0x31C
 382 #define H_RESIZE_HPT_PREPARE    0x36C
 383 #define H_RESIZE_HPT_COMMIT     0x370
 384 #define H_CLEAN_SLB             0x374
 385 #define H_INVALIDATE_PID        0x378
 386 #define H_REGISTER_PROC_TBL     0x37C
 387 #define H_SIGNAL_SYS_RESET      0x380
 388 #define MAX_HCALL_OPCODE        H_SIGNAL_SYS_RESET
 389
 390 /* The hcalls above are standardized in PAPR and implemented by pHyp
 391  * as well.
 392  *
 393  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 394  * We put those into the 0xf000-0xfffc range which is reserved by PAPR
 395  * for "platform-specific" hcalls.
 396  */
 397 #define KVMPPC_HCALL_BASE       0xf000
 398 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 399 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 400 /* Client Architecture support */
 401 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 402 #define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
 403
 404 typedef struct sPAPRDeviceTreeUpdateHeader {
 405     uint32_t version_id;
 406 } sPAPRDeviceTreeUpdateHeader;
 407
 408 #define hcall_dprintf(fmt, ...) \
 409     do { \
 410         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
 411     } while (0)
 412
 413 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 414                                        target_ulong opcode,
 415                                        target_ulong *args);
 416
 417 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 418 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 419                              target_ulong *args);
 420
 421 /* ibm,set-eeh-option */
 422 #define RTAS_EEH_DISABLE                 0
 423 #define RTAS_EEH_ENABLE                  1
 424 #define RTAS_EEH_THAW_IO                 2
 425 #define RTAS_EEH_THAW_DMA                3
 426
 427 /* ibm,get-config-addr-info2 */
 428 #define RTAS_GET_PE_ADDR                 0
 429 #define RTAS_GET_PE_MODE                 1
 430 #define RTAS_PE_MODE_NONE                0
 431 #define RTAS_PE_MODE_NOT_SHARED          1
 432 #define RTAS_PE_MODE_SHARED              2
 433
 434 /* ibm,read-slot-reset-state2 */
 435 #define RTAS_EEH_PE_STATE_NORMAL         0
 436 #define RTAS_EEH_PE_STATE_RESET          1
 437 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
 438 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
 439 #define RTAS_EEH_PE_STATE_UNAVAIL        5
 440 #define RTAS_EEH_NOT_SUPPORT             0
 441 #define RTAS_EEH_SUPPORT                 1
 442 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
 443 #define RTAS_EEH_PE_RECOVER_INFO         0
 444
 445 /* ibm,set-slot-reset */
 446 #define RTAS_SLOT_RESET_DEACTIVATE       0
 447 #define RTAS_SLOT_RESET_HOT              1
 448 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
 449
 450 /* ibm,slot-error-detail */
 451 #define RTAS_SLOT_TEMP_ERR_LOG           1
 452 #define RTAS_SLOT_PERM_ERR_LOG           2
 453
 454 /* RTAS return codes */
 455 #define RTAS_OUT_SUCCESS                        0
 456 #define RTAS_OUT_NO_ERRORS_FOUND                1
 457 #define RTAS_OUT_HW_ERROR                       -1
 458 #define RTAS_OUT_BUSY                           -2
 459 #define RTAS_OUT_PARAM_ERROR                    -3
 460 #define RTAS_OUT_NOT_SUPPORTED                  -3
 461 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
 462 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
 463 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
 464
 465 /* DDW pagesize mask values from ibm,query-pe-dma-window */
 466 #define RTAS_DDW_PGSIZE_4K       0x01
 467 #define RTAS_DDW_PGSIZE_64K      0x02
 468 #define RTAS_DDW_PGSIZE_16M      0x04
 469 #define RTAS_DDW_PGSIZE_32M      0x08
 470 #define RTAS_DDW_PGSIZE_64M      0x10
 471 #define RTAS_DDW_PGSIZE_128M     0x20
 472 #define RTAS_DDW_PGSIZE_256M     0x40
 473 #define RTAS_DDW_PGSIZE_16G      0x80
 474
 475 /* RTAS tokens */
 476 #define RTAS_TOKEN_BASE      0x2000
 477
 478 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 479 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 480 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 481 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 482 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 483 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 484 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 485 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 486 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 487 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 488 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 489 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 490 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 491 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 492 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 493 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 494 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 495 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 496 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 497 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 498 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 499 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 500 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 501 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 502 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 503 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 504 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 505 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 506 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 507 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 508 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 509 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 510 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
 511 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
 512 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
 513 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
 514 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
 515 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
 516 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
 517 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
 518 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
 519 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
 520
 521 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2A)
 522
 523 /* RTAS ibm,get-system-parameter token values */
 524 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 525 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 526 #define RTAS_SYSPARM_UUID                        48
 527
 528 /* RTAS indicator/sensor types
 529  *
 530  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
 531  *
 532  * NOTE: currently only DR-related sensors are implemented here
 533  */
 534 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
 535 #define RTAS_SENSOR_TYPE_DR                     9002
 536 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
 537 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
 538
 539 /* Possible values for the platform-processor-diagnostics-run-mode parameter
 540  * of the RTAS ibm,get-system-parameter call.
 541  */
 542 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
 543 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 544 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 545 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 546
 547 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 548 {
 549     return addr & ~0xF000000000000000ULL;
 550 }
 551
 552 static inline uint32_t rtas_ld(target_ulong phys, int n)
 553 {
 554     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 555 }
 556
 557 static inline uint64_t rtas_ldq(target_ulong phys, int n)
 558 {
 559     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
 560 }
 561
 562 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 563 {
 564     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 565 }
 566
 567 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 568                               uint32_t token,
 569                               uint32_t nargs, target_ulong args,
 570                               uint32_t nret, target_ulong rets);
 571 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 572 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
 573                              uint32_t token, uint32_t nargs, target_ulong args,
 574                              uint32_t nret, target_ulong rets);
 575 void spapr_dt_rtas_tokens(void *fdt, int rtas);
 576 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
 577
 578 #define SPAPR_TCE_PAGE_SHIFT   12
 579 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 580 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 581
 582 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 583 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
 584 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
 585     (0x80000000 | ((phb_index) << 8) | (window_num))
 586 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
 587 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
 588
 589 #define RTAS_ERROR_LOG_MAX      2048
 590
 591 #define RTAS_EVENT_SCAN_RATE    1
 592
 593 /* This helper should be used to encode interrupt specifiers when the related
 594  * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
 595  * VIO devices, RTAS event sources and PHBs).
 596  */
 597 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi)
 598 {
 599     intspec[0] = cpu_to_be32(irq);
 600     intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
 601 }
 602
 603 typedef struct sPAPRTCETable sPAPRTCETable;
 604
 605 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 606 #define SPAPR_TCE_TABLE(obj) \
 607     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
 608
 609 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
 610 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
 611         OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
 612
 613 struct sPAPRTCETable {
 614     DeviceState parent;
 615     uint32_t liobn;
 616     uint32_t nb_table;
 617     uint64_t bus_offset;
 618     uint32_t page_shift;
 619     uint64_t *table;
 620     uint32_t mig_nb_table;
 621     uint64_t *mig_table;
 622     bool bypass;
 623     bool need_vfio;
 624     int fd;
 625     MemoryRegion root;
 626     IOMMUMemoryRegion iommu;
 627     struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
 628     QLIST_ENTRY(sPAPRTCETable) list;
 629 };
 630
 631 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
 632
 633 struct sPAPREventLogEntry {
 634     uint32_t summary;
 635     uint32_t extended_length;
 636     void *extended_log;
 637     QTAILQ_ENTRY(sPAPREventLogEntry) next;
 638 };
 639
 640 void spapr_events_init(sPAPRMachineState *sm);
 641 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
 642 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
 643                                  target_ulong addr, target_ulong size,
 644                                  sPAPROptionVector *ov5_updates);
 645 void close_htab_fd(sPAPRMachineState *spapr);
 646 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr);
 647 void spapr_free_hpt(sPAPRMachineState *spapr);
 648 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
 649 void spapr_tce_table_enable(sPAPRTCETable *tcet,
 650                             uint32_t page_shift, uint64_t bus_offset,
 651                             uint32_t nb_table);
 652 void spapr_tce_table_disable(sPAPRTCETable *tcet);
 653 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
 654
 655 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
 656 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 657                  uint32_t liobn, uint64_t window, uint32_t size);
 658 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 659                       sPAPRTCETable *tcet);
 660 void spapr_pci_switch_vga(bool big_endian);
 661 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
 662 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
 663 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
 664                                        uint32_t count);
 665 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
 666                                           uint32_t count);
 667 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
 668                                             uint32_t count, uint32_t index);
 669 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
 670                                                uint32_t count, uint32_t index);
 671 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
 672 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
 673                           Error **errp);
 674 void spapr_clear_pending_events(sPAPRMachineState *spapr);
 675
 676 /* CPU and LMB DRC release callbacks. */
 677 void spapr_core_release(DeviceState *dev);
 678 void spapr_lmb_release(DeviceState *dev);
 679
 680 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
 681 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
 682
 683 #define TYPE_SPAPR_RNG "spapr-rng"
 684
 685 int spapr_rng_populate_dt(void *fdt);
 686
 687 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
 688
 689 /*
 690  * This defines the maximum number of DIMM slots we can have for sPAPR
 691  * guest. This is not defined by sPAPR but we are defining it to 32 slots
 692  * based on default number of slots provided by PowerPC kernel.
 693  */
 694 #define SPAPR_MAX_RAM_SLOTS     32
 695
 696 /* 1GB alignment for hotplug memory region */
 697 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
 698
 699 /*
 700  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
 701  * property under ibm,dynamic-reconfiguration-memory node.
 702  */
 703 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
 704
 705 /*
 706  * Defines for flag value in ibm,dynamic-memory property under
 707  * ibm,dynamic-reconfiguration-memory node.
 708  */
 709 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
 710 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
 711 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
 712
 713 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
 714
 715 #define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
 716
 717 int spapr_vcpu_id(PowerPCCPU *cpu);
 718 PowerPCCPU *spapr_find_cpu(int vcpu_id);
 719
 720 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
 721                     Error **errp);
 722 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
 723                           bool align, Error **errp);
 724 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
 725 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
 726
 727 #endif /* HW_SPAPR_H */