include/hw/ppc/spapr.h

   1 #ifndef HW_SPAPR_H
   2 #define HW_SPAPR_H
   3
   4 #include "sysemu/dma.h"
   5 #include "hw/boards.h"
   6 #include "hw/ppc/xics.h"
   7 #include "hw/ppc/spapr_drc.h"
   8 #include "hw/mem/pc-dimm.h"
   9 #include "hw/ppc/spapr_ovec.h"
  10
  11 struct VIOsPAPRBus;
  12 struct sPAPRPHBState;
  13 struct sPAPRNVRAM;
  14 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState;
  15 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
  16
  17 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  18 #define SPAPR_ENTRY_POINT       0x100
  19
  20 #define SPAPR_TIMEBASE_FREQ     512000000ULL
  21
  22 typedef struct sPAPRMachineClass sPAPRMachineClass;
  23 typedef struct sPAPRMachineState sPAPRMachineState;
  24
  25 #define TYPE_SPAPR_MACHINE      "spapr-machine"
  26 #define SPAPR_MACHINE(obj) \
  27     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
  28 #define SPAPR_MACHINE_GET_CLASS(obj) \
  29     OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
  30 #define SPAPR_MACHINE_CLASS(klass) \
  31     OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
  32
  33 /**
  34  * sPAPRMachineClass:
  35  */
  36 struct sPAPRMachineClass {
  37     /*< private >*/
  38     MachineClass parent_class;
  39
  40     /*< public >*/
  41     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
  42     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
  43     const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */
  44     void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
  45                           uint64_t *buid, hwaddr *pio,
  46                           hwaddr *mmio32, hwaddr *mmio64,
  47                           unsigned n_dma, uint32_t *liobns, Error **errp);
  48 };
  49
  50 /**
  51  * sPAPRMachineState:
  52  */
  53 struct sPAPRMachineState {
  54     /*< private >*/
  55     MachineState parent_obj;
  56
  57     struct VIOsPAPRBus *vio_bus;
  58     QLIST_HEAD(, sPAPRPHBState) phbs;
  59     struct sPAPRNVRAM *nvram;
  60     XICSState *xics;
  61     DeviceState *rtc;
  62
  63     void *htab;
  64     uint32_t htab_shift;
  65     hwaddr rma_size;
  66     int vrma_adjust;
  67     ssize_t rtas_size;
  68     void *rtas_blob;
  69     long kernel_size;
  70     bool kernel_le;
  71     uint32_t initrd_base;
  72     long initrd_size;
  73     uint64_t rtc_offset; /* Now used only during incoming migration */
  74     struct PPCTimebase tb;
  75     bool has_graphics;
  76     sPAPROptionVector *ov5;         /* QEMU-supported option vectors */
  77     sPAPROptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
  78
  79     uint32_t check_exception_irq;
  80     Notifier epow_notifier;
  81     QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
  82
  83     /* Migration state */
  84     int htab_save_index;
  85     bool htab_first_pass;
  86     int htab_fd;
  87
  88     /* RTAS state */
  89     QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list;
  90
  91     /*< public >*/
  92     char *kvm_type;
  93     MemoryHotplugState hotplug_memory;
  94     Object **cores;
  95 };
  96
  97 #define H_SUCCESS         0
  98 #define H_BUSY            1        /* Hardware busy -- retry later */
  99 #define H_CLOSED          2        /* Resource closed */
 100 #define H_NOT_AVAILABLE   3
 101 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
 102 #define H_PARTIAL         5
 103 #define H_IN_PROGRESS     14       /* Kind of like busy */
 104 #define H_PAGE_REGISTERED 15
 105 #define H_PARTIAL_STORE   16
 106 #define H_PENDING         17       /* returned from H_POLL_PENDING */
 107 #define H_CONTINUE        18       /* Returned from H_Join on success */
 108 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
 109 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
 110                                                  is a good time to retry */
 111 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
 112                                                  is a good time to retry */
 113 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
 114                                                  is a good time to retry */
 115 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
 116                                                  is a good time to retry */
 117 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
 118                                                  is a good time to retry */
 119 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
 120                                                  is a good time to retry */
 121 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
 122 #define H_HARDWARE        -1       /* Hardware error */
 123 #define H_FUNCTION        -2       /* Function not supported */
 124 #define H_PRIVILEGE       -3       /* Caller not privileged */
 125 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
 126 #define H_BAD_MODE        -5       /* Illegal msr value */
 127 #define H_PTEG_FULL       -6       /* PTEG is full */
 128 #define H_NOT_FOUND       -7       /* PTE was not found" */
 129 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
 130 #define H_NO_MEM          -9
 131 #define H_AUTHORITY       -10
 132 #define H_PERMISSION      -11
 133 #define H_DROPPED         -12
 134 #define H_SOURCE_PARM     -13
 135 #define H_DEST_PARM       -14
 136 #define H_REMOTE_PARM     -15
 137 #define H_RESOURCE        -16
 138 #define H_ADAPTER_PARM    -17
 139 #define H_RH_PARM         -18
 140 #define H_RCQ_PARM        -19
 141 #define H_SCQ_PARM        -20
 142 #define H_EQ_PARM         -21
 143 #define H_RT_PARM         -22
 144 #define H_ST_PARM         -23
 145 #define H_SIGT_PARM       -24
 146 #define H_TOKEN_PARM      -25
 147 #define H_MLENGTH_PARM    -27
 148 #define H_MEM_PARM        -28
 149 #define H_MEM_ACCESS_PARM -29
 150 #define H_ATTR_PARM       -30
 151 #define H_PORT_PARM       -31
 152 #define H_MCG_PARM        -32
 153 #define H_VL_PARM         -33
 154 #define H_TSIZE_PARM      -34
 155 #define H_TRACE_PARM      -35
 156
 157 #define H_MASK_PARM       -37
 158 #define H_MCG_FULL        -38
 159 #define H_ALIAS_EXIST     -39
 160 #define H_P_COUNTER       -40
 161 #define H_TABLE_FULL      -41
 162 #define H_ALT_TABLE       -42
 163 #define H_MR_CONDITION    -43
 164 #define H_NOT_ENOUGH_RESOURCES -44
 165 #define H_R_STATE         -45
 166 #define H_RESCINDEND      -46
 167 #define H_P2              -55
 168 #define H_P3              -56
 169 #define H_P4              -57
 170 #define H_P5              -58
 171 #define H_P6              -59
 172 #define H_P7              -60
 173 #define H_P8              -61
 174 #define H_P9              -62
 175 #define H_UNSUPPORTED_FLAG -256
 176 #define H_MULTI_THREADS_ACTIVE -9005
 177
 178
 179 /* Long Busy is a condition that can be returned by the firmware
 180  * when a call cannot be completed now, but the identical call
 181  * should be retried later.  This prevents calls blocking in the
 182  * firmware for long periods of time.  Annoyingly the firmware can return
 183  * a range of return codes, hinting at how long we should wait before
 184  * retrying.  If you don't care for the hint, the macro below is a good
 185  * way to check for the long_busy return codes
 186  */
 187 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 188                             && (x <= H_LONG_BUSY_END_RANGE))
 189
 190 /* Flags */
 191 #define H_LARGE_PAGE      (1ULL<<(63-16))
 192 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 193 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 194 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 195 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 196 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 197 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 198 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 199 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 200 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 201 #define H_ANDCOND         (1ULL<<(63-33))
 202 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 203 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 204 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 205 #define H_COPY_PAGE       (1ULL<<(63-49))
 206 #define H_N               (1ULL<<(63-61))
 207 #define H_PP1             (1ULL<<(63-62))
 208 #define H_PP2             (1ULL<<(63-63))
 209
 210 /* Values for 2nd argument to H_SET_MODE */
 211 #define H_SET_MODE_RESOURCE_SET_CIABR           1
 212 #define H_SET_MODE_RESOURCE_SET_DAWR            2
 213 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 214 #define H_SET_MODE_RESOURCE_LE                  4
 215
 216 /* Flags for H_SET_MODE_RESOURCE_LE */
 217 #define H_SET_MODE_ENDIAN_BIG    0
 218 #define H_SET_MODE_ENDIAN_LITTLE 1
 219
 220 /* VASI States */
 221 #define H_VASI_INVALID    0
 222 #define H_VASI_ENABLED    1
 223 #define H_VASI_ABORTED    2
 224 #define H_VASI_SUSPENDING 3
 225 #define H_VASI_SUSPENDED  4
 226 #define H_VASI_RESUMED    5
 227 #define H_VASI_COMPLETED  6
 228
 229 /* DABRX flags */
 230 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 231 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 232 #define H_DABRX_USER       (1ULL<<(63-63))
 233
 234 /* Each control block has to be on a 4K boundary */
 235 #define H_CB_ALIGNMENT     4096
 236
 237 /* pSeries hypervisor opcodes */
 238 #define H_REMOVE                0x04
 239 #define H_ENTER                 0x08
 240 #define H_READ                  0x0c
 241 #define H_CLEAR_MOD             0x10
 242 #define H_CLEAR_REF             0x14
 243 #define H_PROTECT               0x18
 244 #define H_GET_TCE               0x1c
 245 #define H_PUT_TCE               0x20
 246 #define H_SET_SPRG0             0x24
 247 #define H_SET_DABR              0x28
 248 #define H_PAGE_INIT             0x2c
 249 #define H_SET_ASR               0x30
 250 #define H_ASR_ON                0x34
 251 #define H_ASR_OFF               0x38
 252 #define H_LOGICAL_CI_LOAD       0x3c
 253 #define H_LOGICAL_CI_STORE      0x40
 254 #define H_LOGICAL_CACHE_LOAD    0x44
 255 #define H_LOGICAL_CACHE_STORE   0x48
 256 #define H_LOGICAL_ICBI          0x4c
 257 #define H_LOGICAL_DCBF          0x50
 258 #define H_GET_TERM_CHAR         0x54
 259 #define H_PUT_TERM_CHAR         0x58
 260 #define H_REAL_TO_LOGICAL       0x5c
 261 #define H_HYPERVISOR_DATA       0x60
 262 #define H_EOI                   0x64
 263 #define H_CPPR                  0x68
 264 #define H_IPI                   0x6c
 265 #define H_IPOLL                 0x70
 266 #define H_XIRR                  0x74
 267 #define H_PERFMON               0x7c
 268 #define H_MIGRATE_DMA           0x78
 269 #define H_REGISTER_VPA          0xDC
 270 #define H_CEDE                  0xE0
 271 #define H_CONFER                0xE4
 272 #define H_PROD                  0xE8
 273 #define H_GET_PPP               0xEC
 274 #define H_SET_PPP               0xF0
 275 #define H_PURR                  0xF4
 276 #define H_PIC                   0xF8
 277 #define H_REG_CRQ               0xFC
 278 #define H_FREE_CRQ              0x100
 279 #define H_VIO_SIGNAL            0x104
 280 #define H_SEND_CRQ              0x108
 281 #define H_COPY_RDMA             0x110
 282 #define H_REGISTER_LOGICAL_LAN  0x114
 283 #define H_FREE_LOGICAL_LAN      0x118
 284 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 285 #define H_SEND_LOGICAL_LAN      0x120
 286 #define H_BULK_REMOVE           0x124
 287 #define H_MULTICAST_CTRL        0x130
 288 #define H_SET_XDABR             0x134
 289 #define H_STUFF_TCE             0x138
 290 #define H_PUT_TCE_INDIRECT      0x13C
 291 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 292 #define H_VTERM_PARTNER_INFO    0x150
 293 #define H_REGISTER_VTERM        0x154
 294 #define H_FREE_VTERM            0x158
 295 #define H_RESET_EVENTS          0x15C
 296 #define H_ALLOC_RESOURCE        0x160
 297 #define H_FREE_RESOURCE         0x164
 298 #define H_MODIFY_QP             0x168
 299 #define H_QUERY_QP              0x16C
 300 #define H_REREGISTER_PMR        0x170
 301 #define H_REGISTER_SMR          0x174
 302 #define H_QUERY_MR              0x178
 303 #define H_QUERY_MW              0x17C
 304 #define H_QUERY_HCA             0x180
 305 #define H_QUERY_PORT            0x184
 306 #define H_MODIFY_PORT           0x188
 307 #define H_DEFINE_AQP1           0x18C
 308 #define H_GET_TRACE_BUFFER      0x190
 309 #define H_DEFINE_AQP0           0x194
 310 #define H_RESIZE_MR             0x198
 311 #define H_ATTACH_MCQP           0x19C
 312 #define H_DETACH_MCQP           0x1A0
 313 #define H_CREATE_RPT            0x1A4
 314 #define H_REMOVE_RPT            0x1A8
 315 #define H_REGISTER_RPAGES       0x1AC
 316 #define H_DISABLE_AND_GETC      0x1B0
 317 #define H_ERROR_DATA            0x1B4
 318 #define H_GET_HCA_INFO          0x1B8
 319 #define H_GET_PERF_COUNT        0x1BC
 320 #define H_MANAGE_TRACE          0x1C0
 321 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 322 #define H_QUERY_INT_STATE       0x1E4
 323 #define H_POLL_PENDING          0x1D8
 324 #define H_ILLAN_ATTRIBUTES      0x244
 325 #define H_MODIFY_HEA_QP         0x250
 326 #define H_QUERY_HEA_QP          0x254
 327 #define H_QUERY_HEA             0x258
 328 #define H_QUERY_HEA_PORT        0x25C
 329 #define H_MODIFY_HEA_PORT       0x260
 330 #define H_REG_BCMC              0x264
 331 #define H_DEREG_BCMC            0x268
 332 #define H_REGISTER_HEA_RPAGES   0x26C
 333 #define H_DISABLE_AND_GET_HEA   0x270
 334 #define H_GET_HEA_INFO          0x274
 335 #define H_ALLOC_HEA_RESOURCE    0x278
 336 #define H_ADD_CONN              0x284
 337 #define H_DEL_CONN              0x288
 338 #define H_JOIN                  0x298
 339 #define H_VASI_STATE            0x2A4
 340 #define H_ENABLE_CRQ            0x2B0
 341 #define H_GET_EM_PARMS          0x2B8
 342 #define H_SET_MPP               0x2D0
 343 #define H_GET_MPP               0x2D4
 344 #define H_XIRR_X                0x2FC
 345 #define H_RANDOM                0x300
 346 #define H_SET_MODE              0x31C
 347 #define MAX_HCALL_OPCODE        H_SET_MODE
 348
 349 /* The hcalls above are standardized in PAPR and implemented by pHyp
 350  * as well.
 351  *
 352  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 353  * So far we just need one for H_RTAS, but in future we'll need more
 354  * for extensions like virtio.  We put those into the 0xf000-0xfffc
 355  * range which is reserved by PAPR for "platform-specific" hcalls.
 356  */
 357 #define KVMPPC_HCALL_BASE       0xf000
 358 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 359 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 360 /* Client Architecture support */
 361 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 362 #define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
 363
 364 typedef struct sPAPRDeviceTreeUpdateHeader {
 365     uint32_t version_id;
 366 } sPAPRDeviceTreeUpdateHeader;
 367
 368 #define hcall_dprintf(fmt, ...) \
 369     do { \
 370         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
 371     } while (0)
 372
 373 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 374                                        target_ulong opcode,
 375                                        target_ulong *args);
 376
 377 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 378 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 379                              target_ulong *args);
 380
 381 /* ibm,set-eeh-option */
 382 #define RTAS_EEH_DISABLE                 0
 383 #define RTAS_EEH_ENABLE                  1
 384 #define RTAS_EEH_THAW_IO                 2
 385 #define RTAS_EEH_THAW_DMA                3
 386
 387 /* ibm,get-config-addr-info2 */
 388 #define RTAS_GET_PE_ADDR                 0
 389 #define RTAS_GET_PE_MODE                 1
 390 #define RTAS_PE_MODE_NONE                0
 391 #define RTAS_PE_MODE_NOT_SHARED          1
 392 #define RTAS_PE_MODE_SHARED              2
 393
 394 /* ibm,read-slot-reset-state2 */
 395 #define RTAS_EEH_PE_STATE_NORMAL         0
 396 #define RTAS_EEH_PE_STATE_RESET          1
 397 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
 398 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
 399 #define RTAS_EEH_PE_STATE_UNAVAIL        5
 400 #define RTAS_EEH_NOT_SUPPORT             0
 401 #define RTAS_EEH_SUPPORT                 1
 402 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
 403 #define RTAS_EEH_PE_RECOVER_INFO         0
 404
 405 /* ibm,set-slot-reset */
 406 #define RTAS_SLOT_RESET_DEACTIVATE       0
 407 #define RTAS_SLOT_RESET_HOT              1
 408 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
 409
 410 /* ibm,slot-error-detail */
 411 #define RTAS_SLOT_TEMP_ERR_LOG           1
 412 #define RTAS_SLOT_PERM_ERR_LOG           2
 413
 414 /* RTAS return codes */
 415 #define RTAS_OUT_SUCCESS                        0
 416 #define RTAS_OUT_NO_ERRORS_FOUND                1
 417 #define RTAS_OUT_HW_ERROR                       -1
 418 #define RTAS_OUT_BUSY                           -2
 419 #define RTAS_OUT_PARAM_ERROR                    -3
 420 #define RTAS_OUT_NOT_SUPPORTED                  -3
 421 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
 422 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
 423 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
 424
 425 /* DDW pagesize mask values from ibm,query-pe-dma-window */
 426 #define RTAS_DDW_PGSIZE_4K       0x01
 427 #define RTAS_DDW_PGSIZE_64K      0x02
 428 #define RTAS_DDW_PGSIZE_16M      0x04
 429 #define RTAS_DDW_PGSIZE_32M      0x08
 430 #define RTAS_DDW_PGSIZE_64M      0x10
 431 #define RTAS_DDW_PGSIZE_128M     0x20
 432 #define RTAS_DDW_PGSIZE_256M     0x40
 433 #define RTAS_DDW_PGSIZE_16G      0x80
 434
 435 /* RTAS tokens */
 436 #define RTAS_TOKEN_BASE      0x2000
 437
 438 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 439 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 440 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 441 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 442 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 443 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 444 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 445 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 446 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 447 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 448 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 449 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 450 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 451 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 452 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 453 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 454 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 455 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 456 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 457 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 458 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 459 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 460 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 461 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 462 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 463 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 464 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 465 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 466 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 467 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 468 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 469 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 470 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
 471 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
 472 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
 473 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
 474 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
 475 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
 476 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
 477 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
 478 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
 479 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
 480
 481 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2A)
 482
 483 /* RTAS ibm,get-system-parameter token values */
 484 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 485 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 486 #define RTAS_SYSPARM_UUID                        48
 487
 488 /* RTAS indicator/sensor types
 489  *
 490  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
 491  *
 492  * NOTE: currently only DR-related sensors are implemented here
 493  */
 494 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
 495 #define RTAS_SENSOR_TYPE_DR                     9002
 496 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
 497 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
 498
 499 /* Possible values for the platform-processor-diagnostics-run-mode parameter
 500  * of the RTAS ibm,get-system-parameter call.
 501  */
 502 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
 503 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 504 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 505 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 506
 507 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 508 {
 509     return addr & ~0xF000000000000000ULL;
 510 }
 511
 512 static inline uint32_t rtas_ld(target_ulong phys, int n)
 513 {
 514     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 515 }
 516
 517 static inline uint64_t rtas_ldq(target_ulong phys, int n)
 518 {
 519     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
 520 }
 521
 522 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 523 {
 524     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 525 }
 526
 527 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
 528                               uint32_t token,
 529                               uint32_t nargs, target_ulong args,
 530                               uint32_t nret, target_ulong rets);
 531 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 532 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
 533                              uint32_t token, uint32_t nargs, target_ulong args,
 534                              uint32_t nret, target_ulong rets);
 535 void spapr_dt_rtas_tokens(void *fdt, int rtas);
 536 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
 537
 538 #define SPAPR_TCE_PAGE_SHIFT   12
 539 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 540 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 541
 542 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 543 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
 544 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
 545     (0x80000000 | ((phb_index) << 8) | (window_num))
 546 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
 547 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
 548
 549 #define RTAS_ERROR_LOG_MAX      2048
 550
 551 #define RTAS_EVENT_SCAN_RATE    1
 552
 553 typedef struct sPAPRTCETable sPAPRTCETable;
 554
 555 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 556 #define SPAPR_TCE_TABLE(obj) \
 557     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
 558
 559 struct sPAPRTCETable {
 560     DeviceState parent;
 561     uint32_t liobn;
 562     uint32_t nb_table;
 563     uint64_t bus_offset;
 564     uint32_t page_shift;
 565     uint64_t *table;
 566     uint32_t mig_nb_table;
 567     uint64_t *mig_table;
 568     bool bypass;
 569     bool need_vfio;
 570     int fd;
 571     MemoryRegion root, iommu;
 572     struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
 573     QLIST_ENTRY(sPAPRTCETable) list;
 574 };
 575
 576 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
 577
 578 struct sPAPREventLogEntry {
 579     int log_type;
 580     bool exception;
 581     void *data;
 582     QTAILQ_ENTRY(sPAPREventLogEntry) next;
 583 };
 584
 585 void spapr_events_init(sPAPRMachineState *sm);
 586 void spapr_dt_events(void *fdt, uint32_t check_exception_irq);
 587 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
 588                                  target_ulong addr, target_ulong size,
 589                                  bool cpu_update);
 590 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
 591 void spapr_tce_table_enable(sPAPRTCETable *tcet,
 592                             uint32_t page_shift, uint64_t bus_offset,
 593                             uint32_t nb_table);
 594 void spapr_tce_table_disable(sPAPRTCETable *tcet);
 595 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
 596
 597 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
 598 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 599                  uint32_t liobn, uint64_t window, uint32_t size);
 600 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 601                       sPAPRTCETable *tcet);
 602 void spapr_pci_switch_vga(bool big_endian);
 603 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
 604 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
 605 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
 606                                        uint32_t count);
 607 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
 608                                           uint32_t count);
 609 void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp);
 610 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
 611                                     sPAPRMachineState *spapr);
 612
 613 /* rtas-configure-connector state */
 614 struct sPAPRConfigureConnectorState {
 615     uint32_t drc_index;
 616     int fdt_offset;
 617     int fdt_depth;
 618     QTAILQ_ENTRY(sPAPRConfigureConnectorState) next;
 619 };
 620
 621 void spapr_ccs_reset_hook(void *opaque);
 622
 623 #define TYPE_SPAPR_RTC "spapr-rtc"
 624 #define TYPE_SPAPR_RNG "spapr-rng"
 625
 626 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns);
 627 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset);
 628
 629 int spapr_rng_populate_dt(void *fdt);
 630
 631 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
 632
 633 /*
 634  * This defines the maximum number of DIMM slots we can have for sPAPR
 635  * guest. This is not defined by sPAPR but we are defining it to 32 slots
 636  * based on default number of slots provided by PowerPC kernel.
 637  */
 638 #define SPAPR_MAX_RAM_SLOTS     32
 639
 640 /* 1GB alignment for hotplug memory region */
 641 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
 642
 643 /*
 644  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
 645  * property under ibm,dynamic-reconfiguration-memory node.
 646  */
 647 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
 648
 649 /*
 650  * Defines for flag value in ibm,dynamic-memory property under
 651  * ibm,dynamic-reconfiguration-memory node.
 652  */
 653 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
 654 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
 655 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
 656
 657 #endif /* HW_SPAPR_H */