include/hw/riscv/opentitan.h

   1 /*
   2  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_OPENTITAN_H
  20 #define HW_OPENTITAN_H
  21
  22 #include "hw/riscv/riscv_hart.h"
  23 #include "hw/intc/ibex_plic.h"
  24 #include "hw/char/ibex_uart.h"
  25 #include "qom/object.h"
  26
  27 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
  28 typedef struct LowRISCIbexSoCState LowRISCIbexSoCState;
  29 DECLARE_INSTANCE_CHECKER(LowRISCIbexSoCState, RISCV_IBEX_SOC,
  30                          TYPE_RISCV_IBEX_SOC)
  31
  32 struct LowRISCIbexSoCState {
  33     /*< private >*/
  34     SysBusDevice parent_obj;
  35
  36     /*< public >*/
  37     RISCVHartArrayState cpus;
  38     IbexPlicState plic;
  39     IbexUartState uart;
  40
  41     MemoryRegion flash_mem;
  42     MemoryRegion rom;
  43 };
  44
  45 typedef struct OpenTitanState {
  46     /*< private >*/
  47     SysBusDevice parent_obj;
  48
  49     /*< public >*/
  50     LowRISCIbexSoCState soc;
  51 } OpenTitanState;
  52
  53 enum {
  54     IBEX_DEV_ROM,
  55     IBEX_DEV_RAM,
  56     IBEX_DEV_FLASH,
  57     IBEX_DEV_UART,
  58     IBEX_DEV_GPIO,
  59     IBEX_DEV_SPI,
  60     IBEX_DEV_FLASH_CTRL,
  61     IBEX_DEV_RV_TIMER,
  62     IBEX_DEV_AES,
  63     IBEX_DEV_HMAC,
  64     IBEX_DEV_PLIC,
  65     IBEX_DEV_PWRMGR,
  66     IBEX_DEV_RSTMGR,
  67     IBEX_DEV_CLKMGR,
  68     IBEX_DEV_PINMUX,
  69     IBEX_DEV_ALERT_HANDLER,
  70     IBEX_DEV_NMI_GEN,
  71     IBEX_DEV_USBDEV,
  72     IBEX_DEV_PADCTRL,
  73 };
  74
  75 enum {
  76     IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
  77     IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
  78     IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
  79     IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
  80     IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
  81     IBEX_UART_TX_EMPTY_IRQ = 0x23,
  82     IBEX_UART_RX_WATERMARK_IRQ = 0x22,
  83     IBEX_UART_TX_WATERMARK_IRQ = 0x21,
  84 };
  85
  86 #endif