include/hw/riscv/sifive_prci.h

   1 /*
   2  * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_PRCI_H
  20 #define HW_SIFIVE_PRCI_H
  21
  22 #include "hw/sysbus.h"
  23
  24 enum {
  25     SIFIVE_PRCI_HFROSCCFG   = 0x0,
  26     SIFIVE_PRCI_HFXOSCCFG   = 0x4,
  27     SIFIVE_PRCI_PLLCFG      = 0x8,
  28     SIFIVE_PRCI_PLLOUTDIV   = 0xC
  29 };
  30
  31 enum {
  32     SIFIVE_PRCI_HFROSCCFG_RDY   = (1 << 31),
  33     SIFIVE_PRCI_HFROSCCFG_EN    = (1 << 30)
  34 };
  35
  36 enum {
  37     SIFIVE_PRCI_HFXOSCCFG_RDY   = (1 << 31),
  38     SIFIVE_PRCI_HFXOSCCFG_EN    = (1 << 30)
  39 };
  40
  41 enum {
  42     SIFIVE_PRCI_PLLCFG_PLLSEL   = (1 << 16),
  43     SIFIVE_PRCI_PLLCFG_REFSEL   = (1 << 17),
  44     SIFIVE_PRCI_PLLCFG_BYPASS   = (1 << 18),
  45     SIFIVE_PRCI_PLLCFG_LOCK     = (1 << 31)
  46 };
  47
  48 enum {
  49     SIFIVE_PRCI_PLLOUTDIV_DIV1  = (1 << 8)
  50 };
  51
  52 #define TYPE_SIFIVE_PRCI "riscv.sifive.prci"
  53
  54 #define SIFIVE_PRCI(obj) \
  55     OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI)
  56
  57 typedef struct SiFivePRCIState {
  58     /*< private >*/
  59     SysBusDevice parent_obj;
  60
  61     /*< public >*/
  62     MemoryRegion mmio;
  63     uint32_t hfrosccfg;
  64     uint32_t hfxosccfg;
  65     uint32_t pllcfg;
  66     uint32_t plloutdiv;
  67 } SiFivePRCIState;
  68
  69 DeviceState *sifive_prci_create(hwaddr addr);
  70
  71 #endif