2 * SiFive U series machine interface
4 * Copyright (c) 2017 SiFive, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "hw/net/cadence_gem.h"
23 #include "hw/riscv/riscv_hart.h"
24 #include "hw/riscv/sifive_cpu.h"
26 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
27 #define RISCV_U_SOC(obj) \
28 OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
30 typedef struct SiFiveUSoCState
{
32 SysBusDevice parent_obj
;
35 CPUClusterState e_cluster
;
36 CPUClusterState u_cluster
;
37 RISCVHartArrayState e_cpus
;
38 RISCVHartArrayState u_cpus
;
43 typedef struct SiFiveUState
{
45 SysBusDevice parent_obj
;
65 SIFIVE_U_UART0_IRQ
= 3,
66 SIFIVE_U_UART1_IRQ
= 4,
67 SIFIVE_U_GEM_IRQ
= 0x35
71 SIFIVE_U_CLOCK_FREQ
= 1000000000,
72 SIFIVE_U_HFCLK_FREQ
= 33333333,
73 SIFIVE_U_RTCCLK_FREQ
= 1000000,
74 SIFIVE_U_GEM_CLOCK_FREQ
= 125000000
77 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
78 #define SIFIVE_U_COMPUTE_CPU_COUNT 4
80 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
81 #define SIFIVE_U_PLIC_NUM_SOURCES 54
82 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
83 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
84 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
85 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
86 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
87 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
88 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000