2 * SiFive U series machine interface
4 * Copyright (c) 2017 SiFive, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "hw/net/cadence_gem.h"
23 #include "hw/riscv/riscv_hart.h"
24 #include "hw/riscv/sifive_cpu.h"
25 #include "hw/riscv/sifive_gpio.h"
26 #include "hw/riscv/sifive_u_prci.h"
27 #include "hw/riscv/sifive_u_otp.h"
29 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
30 #define RISCV_U_SOC(obj) \
31 OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
33 typedef struct SiFiveUSoCState
{
35 DeviceState parent_obj
;
38 CPUClusterState e_cluster
;
39 CPUClusterState u_cluster
;
40 RISCVHartArrayState e_cpus
;
41 RISCVHartArrayState u_cpus
;
43 SiFiveUPRCIState prci
;
51 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
52 #define RISCV_U_MACHINE(obj) \
53 OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
55 typedef struct SiFiveUState
{
57 MachineState parent_obj
;
89 SIFIVE_U_UART0_IRQ
= 4,
90 SIFIVE_U_UART1_IRQ
= 5,
91 SIFIVE_U_GPIO_IRQ0
= 7,
92 SIFIVE_U_GPIO_IRQ1
= 8,
93 SIFIVE_U_GPIO_IRQ2
= 9,
94 SIFIVE_U_GPIO_IRQ3
= 10,
95 SIFIVE_U_GPIO_IRQ4
= 11,
96 SIFIVE_U_GPIO_IRQ5
= 12,
97 SIFIVE_U_GPIO_IRQ6
= 13,
98 SIFIVE_U_GPIO_IRQ7
= 14,
99 SIFIVE_U_GPIO_IRQ8
= 15,
100 SIFIVE_U_GPIO_IRQ9
= 16,
101 SIFIVE_U_GPIO_IRQ10
= 17,
102 SIFIVE_U_GPIO_IRQ11
= 18,
103 SIFIVE_U_GPIO_IRQ12
= 19,
104 SIFIVE_U_GPIO_IRQ13
= 20,
105 SIFIVE_U_GPIO_IRQ14
= 21,
106 SIFIVE_U_GPIO_IRQ15
= 22,
107 SIFIVE_U_GEM_IRQ
= 0x35
111 SIFIVE_U_HFCLK_FREQ
= 33333333,
112 SIFIVE_U_RTCCLK_FREQ
= 1000000
116 MSEL_MEMMAP_QSPI0_FLASH
= 1,
117 MSEL_L2LIM_QSPI0_FLASH
= 6,
118 MSEL_L2LIM_QSPI2_SD
= 11
121 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
122 #define SIFIVE_U_COMPUTE_CPU_COUNT 4
124 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
125 #define SIFIVE_U_PLIC_NUM_SOURCES 54
126 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
127 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
128 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
129 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
130 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
131 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
132 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000