include/hw/riscv/sifive_u.h

   1 /*
   2  * SiFive U series machine interface
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_U_H
  20 #define HW_SIFIVE_U_H
  21
  22 #include "hw/net/cadence_gem.h"
  23 #include "hw/riscv/riscv_hart.h"
  24 #include "hw/riscv/sifive_cpu.h"
  25 #include "hw/riscv/sifive_u_prci.h"
  26
  27 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
  28 #define RISCV_U_SOC(obj) \
  29     OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
  30
  31 typedef struct SiFiveUSoCState {
  32     /*< private >*/
  33     SysBusDevice parent_obj;
  34
  35     /*< public >*/
  36     CPUClusterState e_cluster;
  37     CPUClusterState u_cluster;
  38     RISCVHartArrayState e_cpus;
  39     RISCVHartArrayState u_cpus;
  40     DeviceState *plic;
  41     SiFiveUPRCIState prci;
  42     CadenceGEMState gem;
  43 } SiFiveUSoCState;
  44
  45 typedef struct SiFiveUState {
  46     /*< private >*/
  47     SysBusDevice parent_obj;
  48
  49     /*< public >*/
  50     SiFiveUSoCState soc;
  51     void *fdt;
  52     int fdt_size;
  53 } SiFiveUState;
  54
  55 enum {
  56     SIFIVE_U_DEBUG,
  57     SIFIVE_U_MROM,
  58     SIFIVE_U_CLINT,
  59     SIFIVE_U_PLIC,
  60     SIFIVE_U_PRCI,
  61     SIFIVE_U_UART0,
  62     SIFIVE_U_UART1,
  63     SIFIVE_U_DRAM,
  64     SIFIVE_U_GEM
  65 };
  66
  67 enum {
  68     SIFIVE_U_UART0_IRQ = 3,
  69     SIFIVE_U_UART1_IRQ = 4,
  70     SIFIVE_U_GEM_IRQ = 0x35
  71 };
  72
  73 enum {
  74     SIFIVE_U_CLOCK_FREQ = 1000000000,
  75     SIFIVE_U_HFCLK_FREQ = 33333333,
  76     SIFIVE_U_RTCCLK_FREQ = 1000000,
  77     SIFIVE_U_GEM_CLOCK_FREQ = 125000000
  78 };
  79
  80 #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
  81 #define SIFIVE_U_COMPUTE_CPU_COUNT      4
  82
  83 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
  84 #define SIFIVE_U_PLIC_NUM_SOURCES 54
  85 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
  86 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
  87 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
  88 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
  89 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
  90 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
  91 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
  92
  93 #endif