include/hw/southbridge/piix.h

   1 /*
   2  * QEMU PIIX South Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   8  * See the COPYING file in the top-level directory.
   9  *
  10  */
  11
  12 #ifndef HW_SOUTHBRIDGE_PIIX_H
  13 #define HW_SOUTHBRIDGE_PIIX_H
  14
  15 #include "hw/pci/pci.h"
  16 #include "qom/object.h"
  17 #include "hw/acpi/piix4.h"
  18
  19 PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
  20                               bool smm_enabled);
  21
  22 /* PIRQRC[A:D]: PIRQx Route Control Registers */
  23 #define PIIX_PIRQCA 0x60
  24 #define PIIX_PIRQCB 0x61
  25 #define PIIX_PIRQCC 0x62
  26 #define PIIX_PIRQCD 0x63
  27
  28 /*
  29  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  30  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  31  */
  32 #define PIIX_RCR_IOPORT 0xcf9
  33
  34 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  35 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  36
  37 struct PIIXState {
  38     PCIDevice dev;
  39
  40     /*
  41      * bitmap to track pic levels.
  42      * The pic level is the logical OR of all the PCI irqs mapped to it
  43      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  44      *
  45      * PIRQ is mapped to PIC pins, we track it by
  46      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  47      * pic_irq * PIIX_NUM_PIRQS + pirq
  48      */
  49 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  50 #error "unable to encode pic state in 64bit in pic_levels."
  51 #endif
  52     uint64_t pic_levels;
  53
  54     qemu_irq *pic;
  55
  56     /* This member isn't used. Just for save/load compatibility */
  57     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  58
  59     /* Reset Control Register contents */
  60     uint8_t rcr;
  61
  62     /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
  63     MemoryRegion rcr_mem;
  64 };
  65 typedef struct PIIXState PIIX3State;
  66
  67 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
  68 DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
  69                          TYPE_PIIX3_PCI_DEVICE)
  70
  71 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
  72
  73 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
  74
  75 #endif