include/hw/watchdog/wdt_imx2.h

   1 /*
   2  * Copyright (c) 2017, Impinj, Inc.
   3  *
   4  * i.MX2 Watchdog IP block
   5  *
   6  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef IMX2_WDT_H
  13 #define IMX2_WDT_H
  14
  15 #include "qemu/bitops.h"
  16 #include "hw/sysbus.h"
  17 #include "hw/irq.h"
  18 #include "hw/ptimer.h"
  19 #include "qom/object.h"
  20
  21 #define TYPE_IMX2_WDT "imx2.wdt"
  22 typedef struct IMX2WdtState IMX2WdtState;
  23 DECLARE_INSTANCE_CHECKER(IMX2WdtState, IMX2_WDT,
  24                          TYPE_IMX2_WDT)
  25
  26 enum IMX2WdtRegisters {
  27     IMX2_WDT_WCR  = 0x0000, /* Control Register */
  28     IMX2_WDT_WSR  = 0x0002, /* Service Register */
  29     IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
  30     IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
  31     IMX2_WDT_WMCR = 0x0008, /* Misc Register */
  32 };
  33
  34 #define IMX2_WDT_MMIO_SIZE 0x000a
  35
  36 /* Control Register definitions */
  37 #define IMX2_WDT_WCR_WT         (0xFF << 8) /* Watchdog Timeout Field */
  38 #define IMX2_WDT_WCR_WDW        BIT(7)      /* WDOG Disable for Wait */
  39 #define IMX2_WDT_WCR_WDA        BIT(5)      /* WDOG Assertion */
  40 #define IMX2_WDT_WCR_SRS        BIT(4)      /* Software Reset Signal */
  41 #define IMX2_WDT_WCR_WDT        BIT(3)      /* WDOG Timeout Assertion */
  42 #define IMX2_WDT_WCR_WDE        BIT(2)      /* Watchdog Enable */
  43 #define IMX2_WDT_WCR_WDBG       BIT(1)      /* Watchdog Debug Enable */
  44 #define IMX2_WDT_WCR_WDZST      BIT(0)      /* Watchdog Timer Suspend */
  45
  46 #define IMX2_WDT_WCR_LOCK_MASK  (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
  47                                  | IMX2_WDT_WCR_WDW)
  48
  49 /* Service Register definitions */
  50 #define IMX2_WDT_SEQ1           0x5555      /* service sequence 1 */
  51 #define IMX2_WDT_SEQ2           0xAAAA      /* service sequence 2 */
  52
  53 /* Reset Status Register definitions */
  54 #define IMX2_WDT_WRSR_TOUT      BIT(1)      /* Reset due to Timeout */
  55 #define IMX2_WDT_WRSR_SFTW      BIT(0)      /* Reset due to software reset */
  56
  57 /* Interrupt Control Register definitions */
  58 #define IMX2_WDT_WICR_WIE       BIT(15)     /* Interrupt Enable */
  59 #define IMX2_WDT_WICR_WTIS      BIT(14)     /* Interrupt Status */
  60 #define IMX2_WDT_WICR_WICT      0xff        /* Interrupt Timeout */
  61 #define IMX2_WDT_WICR_WICT_DEF  0x04        /* Default interrupt timeout (2s) */
  62
  63 #define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
  64
  65 /* Misc Control Register definitions */
  66 #define IMX2_WDT_WMCR_PDE       BIT(0)      /* Power-Down Enable */
  67
  68 struct IMX2WdtState {
  69     /* <private> */
  70     SysBusDevice parent_obj;
  71
  72     /*< public >*/
  73     MemoryRegion mmio;
  74     qemu_irq irq;
  75
  76     struct ptimer_state *timer;
  77     struct ptimer_state *itimer;
  78
  79     bool pretimeout_support;
  80     bool wicr_locked;
  81
  82     uint16_t wcr;
  83     uint16_t wsr;
  84     uint16_t wrsr;
  85     uint16_t wicr;
  86     uint16_t wmcr;
  87
  88     bool wcr_locked;            /* affects WDZST, WDBG, and WDW */
  89     bool wcr_wde_locked;        /* affects WDE */
  90     bool wcr_wdt_locked;        /* affects WDT (never cleared) */
  91 };
  92
  93 #endif /* IMX2_WDT_H */