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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2015 Linaro Ltd.
4 * Author: Shannon Zhao <shannon.zhao@linaro.org>
5 */
6
7 #ifndef __ASM_ARM_KVM_PMU_H
8 #define __ASM_ARM_KVM_PMU_H
9
10 #include <linux/perf_event.h>
11 #include <asm/perf_event.h>
12
13 #define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
14
15 #ifdef CONFIG_KVM_ARM_PMU
16
17 struct kvm_pmc {
18 u8 idx; /* index into the pmu->pmc array */
19 struct perf_event *perf_event;
20 u64 bitmask;
21 };
22
23 struct kvm_pmu {
24 int irq_num;
25 struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
26 bool ready;
27 bool created;
28 bool irq_level;
29 };
30
31 #define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
32 #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
33 u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
34 void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
35 u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
36 void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
37 void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
38 void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
39 void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
40 void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
41 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
42 bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
43 void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
44 void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
45 void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
46 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
47 u64 select_idx);
48 bool kvm_arm_support_pmu_v3(void);
49 int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
50 struct kvm_device_attr *attr);
51 int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
52 struct kvm_device_attr *attr);
53 int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
54 struct kvm_device_attr *attr);
55 int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
56 #else
57 struct kvm_pmu {
58 };
59
60 #define kvm_arm_pmu_v3_ready(v) (false)
61 #define kvm_arm_pmu_irq_initialized(v) (false)
62 static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
63 u64 select_idx)
64 {
65 return 0;
66 }
67 static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
68 u64 select_idx, u64 val) {}
69 static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
70 {
71 return 0;
72 }
73 static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
74 static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
75 static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
76 static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
77 static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
78 static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
79 static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
80 {
81 return false;
82 }
83 static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
84 static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
85 static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
86 static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
87 u64 data, u64 select_idx) {}
88 static inline bool kvm_arm_support_pmu_v3(void) { return false; }
89 static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
90 struct kvm_device_attr *attr)
91 {
92 return -ENXIO;
93 }
94 static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
95 struct kvm_device_attr *attr)
96 {
97 return -ENXIO;
98 }
99 static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
100 struct kvm_device_attr *attr)
101 {
102 return -ENXIO;
103 }
104 static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
105 {
106 return 0;
107 }
108 #endif
109
110 #endif