2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __KVM_ARM_VGIC_H
17 #define __KVM_ARM_VGIC_H
19 #include <linux/kernel.h>
20 #include <linux/kvm.h>
21 #include <linux/irqreturn.h>
22 #include <linux/spinlock.h>
23 #include <linux/static_key.h>
24 #include <linux/types.h>
25 #include <kvm/iodev.h>
26 #include <linux/list.h>
27 #include <linux/jump_label.h>
29 #include <linux/irqchip/arm-gic-v4.h>
31 #define VGIC_V3_MAX_CPUS 255
32 #define VGIC_V2_MAX_CPUS 8
33 #define VGIC_NR_IRQS_LEGACY 256
34 #define VGIC_NR_SGIS 16
35 #define VGIC_NR_PPIS 16
36 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
37 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
38 #define VGIC_MAX_SPI 1019
39 #define VGIC_MAX_RESERVED 1023
40 #define VGIC_MIN_LPI 8192
41 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
43 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
44 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
45 (irq) <= VGIC_MAX_SPI)
48 VGIC_V2
, /* Good ol' GICv2 */
49 VGIC_V3
, /* New fancy GICv3 */
52 /* same for all guests, as depending only on the _host's_ GIC model */
54 /* type of the host GIC */
57 /* Physical address of vgic virtual cpu interface */
58 phys_addr_t vcpu_base
;
61 void __iomem
*vcpu_base_va
;
63 /* virtual control interface mapping */
64 void __iomem
*vctrl_base
;
66 /* Number of implemented list registers */
69 /* Maintenance IRQ number */
70 unsigned int maint_irq
;
72 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
75 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
76 bool can_emulate_gicv2
;
78 /* Hardware has GICv4? */
81 /* GIC system register CPU interface */
82 struct static_key_false gicv3_cpuif
;
87 extern struct vgic_global kvm_vgic_global_state
;
89 #define VGIC_V2_MAX_LRS (1 << 6)
90 #define VGIC_V3_MAX_LRS 16
91 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
93 enum vgic_irq_config
{
99 spinlock_t irq_lock
; /* Protects the content of the struct */
100 struct list_head lpi_list
; /* Used to link all LPIs together */
101 struct list_head ap_list
;
103 struct kvm_vcpu
*vcpu
; /* SGIs and PPIs: The VCPU
104 * SPIs and LPIs: The VCPU whose ap_list
108 struct kvm_vcpu
*target_vcpu
; /* The VCPU that this interrupt should
109 * be sent to, as a result of the
110 * targets reg (v2) or the
114 u32 intid
; /* Guest visible INTID */
115 bool line_level
; /* Level only */
116 bool pending_latch
; /* The pending latch state used to calculate
117 * the pending state for both level
118 * and edge triggered IRQs. */
119 bool active
; /* not used for LPIs */
121 bool hw
; /* Tied to HW IRQ */
122 struct kref refcount
; /* Used for LPIs */
123 u32 hwintid
; /* HW INTID number */
124 unsigned int host_irq
; /* linux irq corresponding to hwintid */
126 u8 targets
; /* GICv2 target VCPUs mask */
127 u32 mpidr
; /* GICv3 target VCPU */
129 u8 source
; /* GICv2 SGIs only */
131 enum vgic_irq_config config
; /* Level or edge */
133 void *owner
; /* Opaque pointer to reserve an interrupt
134 for in-kernel devices. */
137 struct vgic_register_region
;
147 struct vgic_io_device
{
150 struct kvm_vcpu
*redist_vcpu
;
151 struct vgic_its
*its
;
153 const struct vgic_register_region
*regions
;
154 enum iodev_type iodev_type
;
156 struct kvm_io_device dev
;
160 /* The base address of the ITS control register frame */
164 struct vgic_io_device iodev
;
165 struct kvm_device
*dev
;
167 /* These registers correspond to GITS_BASER{0,1} */
168 u64 baser_device_table
;
169 u64 baser_coll_table
;
171 /* Protects the command queue */
172 struct mutex cmd_lock
;
177 /* migration ABI revision in use */
180 /* Protects the device and collection lists */
181 struct mutex its_lock
;
182 struct list_head device_list
;
183 struct list_head collection_list
;
186 struct vgic_state_iter
;
193 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
196 /* Do injected MSIs require an additional device ID? */
197 bool msis_require_devid
;
201 /* TODO: Consider moving to global state */
202 /* Virtual control interface mapping */
203 void __iomem
*vctrl_base
;
205 /* base addresses in guest physical address space: */
206 gpa_t vgic_dist_base
; /* distributor */
208 /* either a GICv2 CPU interface */
210 /* or a number of GICv3 redistributor regions */
212 gpa_t vgic_redist_base
;
213 gpa_t vgic_redist_free_offset
;
217 /* distributor enabled */
220 struct vgic_irq
*spis
;
222 struct vgic_io_device dist_iodev
;
227 * Contains the attributes and gpa of the LPI configuration table.
228 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
229 * one address across all redistributors.
230 * GICv3 spec: 6.1.2 "LPI Configuration tables"
234 /* Protects the lpi_list and the count value below. */
235 spinlock_t lpi_list_lock
;
236 struct list_head lpi_list_head
;
239 /* used by vgic-debug */
240 struct vgic_state_iter
*iter
;
243 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
244 * array, the property table pointer as well as allocation
245 * data. This essentially ties the Linux IRQ core and ITS
246 * together, and avoids leaking KVM's data structures anywhere
249 struct its_vm its_vm
;
252 struct vgic_v2_cpu_if
{
255 u64 vgic_elrsr
; /* Saved only */
257 u32 vgic_lr
[VGIC_V2_MAX_LRS
];
260 struct vgic_v3_cpu_if
{
263 u32 vgic_sre
; /* Restored only, change ignored */
264 u32 vgic_elrsr
; /* Saved only */
267 u64 vgic_lr
[VGIC_V3_MAX_LRS
];
270 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
271 * pending table pointer, the its_vm pointer and a few other
272 * HW specific things. As for the its_vm structure, this is
273 * linking the Linux IRQ subsystem and the ITS together.
275 struct its_vpe its_vpe
;
279 /* CPU vif control registers for world switch */
281 struct vgic_v2_cpu_if vgic_v2
;
282 struct vgic_v3_cpu_if vgic_v3
;
285 unsigned int used_lrs
;
286 struct vgic_irq private_irqs
[VGIC_NR_PRIVATE_IRQS
];
288 spinlock_t ap_list_lock
; /* Protects the ap_list */
291 * List of IRQs that this VCPU should consider because they are either
292 * Active or Pending (hence the name; AP list), or because they recently
293 * were one of the two and need to be migrated off this list to another
296 struct list_head ap_list_head
;
299 * Members below are used with GICv3 emulation only and represent
300 * parts of the redistributor.
302 struct vgic_io_device rd_iodev
;
303 struct vgic_io_device sgi_iodev
;
305 /* Contains the attributes and gpa of the LPI pending tables. */
310 /* Cache guest priority bits */
313 /* Cache guest interrupt ID bits */
317 extern struct static_key_false vgic_v2_cpuif_trap
;
318 extern struct static_key_false vgic_v3_cpuif_trap
;
320 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
);
321 void kvm_vgic_early_init(struct kvm
*kvm
);
322 int kvm_vgic_vcpu_init(struct kvm_vcpu
*vcpu
);
323 int kvm_vgic_create(struct kvm
*kvm
, u32 type
);
324 void kvm_vgic_destroy(struct kvm
*kvm
);
325 void kvm_vgic_vcpu_early_init(struct kvm_vcpu
*vcpu
);
326 void kvm_vgic_vcpu_destroy(struct kvm_vcpu
*vcpu
);
327 int kvm_vgic_map_resources(struct kvm
*kvm
);
328 int kvm_vgic_hyp_init(void);
329 void kvm_vgic_init_cpu_hardware(void);
331 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int intid
,
332 bool level
, void *owner
);
333 int kvm_vgic_map_phys_irq(struct kvm_vcpu
*vcpu
, unsigned int host_irq
,
335 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu
*vcpu
, unsigned int vintid
);
336 bool kvm_vgic_map_is_active(struct kvm_vcpu
*vcpu
, unsigned int vintid
);
338 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
);
340 void kvm_vgic_load(struct kvm_vcpu
*vcpu
);
341 void kvm_vgic_put(struct kvm_vcpu
*vcpu
);
343 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
344 #define vgic_initialized(k) ((k)->arch.vgic.initialized)
345 #define vgic_ready(k) ((k)->arch.vgic.ready)
346 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
347 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
349 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu
*vcpu
);
350 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
);
351 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
);
353 void vgic_v3_dispatch_sgi(struct kvm_vcpu
*vcpu
, u64 reg
);
356 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
358 * The host's GIC naturally limits the maximum amount of VCPUs a guest
361 static inline int kvm_vgic_get_max_vcpus(void)
363 return kvm_vgic_global_state
.max_gic_vcpus
;
366 int kvm_send_userspace_msi(struct kvm
*kvm
, struct kvm_msi
*msi
);
369 * kvm_vgic_setup_default_irq_routing:
370 * Setup a default flat gsi routing table mapping all SPIs
372 int kvm_vgic_setup_default_irq_routing(struct kvm
*kvm
);
374 int kvm_vgic_set_owner(struct kvm_vcpu
*vcpu
, unsigned int intid
, void *owner
);
376 struct kvm_kernel_irq_routing_entry
;
378 int kvm_vgic_v4_set_forwarding(struct kvm
*kvm
, int irq
,
379 struct kvm_kernel_irq_routing_entry
*irq_entry
);
381 int kvm_vgic_v4_unset_forwarding(struct kvm
*kvm
, int irq
,
382 struct kvm_kernel_irq_routing_entry
*irq_entry
);
384 void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu
*vcpu
);
385 void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu
*vcpu
);
387 #endif /* __KVM_ARM_VGIC_H */