include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_H
  17 #define __KVM_ARM_VGIC_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/kvm.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/static_key.h>
  24 #include <linux/types.h>
  25 #include <kvm/iodev.h>
  26 #include <linux/list.h>
  27 #include <linux/jump_label.h>
  28
  29 #define VGIC_V3_MAX_CPUS        255
  30 #define VGIC_V2_MAX_CPUS        8
  31 #define VGIC_NR_IRQS_LEGACY     256
  32 #define VGIC_NR_SGIS            16
  33 #define VGIC_NR_PPIS            16
  34 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  35 #define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  36 #define VGIC_MAX_SPI            1019
  37 #define VGIC_MAX_RESERVED       1023
  38 #define VGIC_MIN_LPI            8192
  39 #define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
  40
  41 enum vgic_type {
  42         VGIC_V2,                /* Good ol' GICv2 */
  43         VGIC_V3,                /* New fancy GICv3 */
  44 };
  45
  46 /* same for all guests, as depending only on the _host's_ GIC model */
  47 struct vgic_global {
  48         /* type of the host GIC */
  49         enum vgic_type          type;
  50
  51         /* Physical address of vgic virtual cpu interface */
  52         phys_addr_t             vcpu_base;
  53
  54         /* GICV mapping */
  55         void __iomem            *vcpu_base_va;
  56
  57         /* virtual control interface mapping */
  58         void __iomem            *vctrl_base;
  59
  60         /* Number of implemented list registers */
  61         int                     nr_lr;
  62
  63         /* Maintenance IRQ number */
  64         unsigned int            maint_irq;
  65
  66         /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  67         int                     max_gic_vcpus;
  68
  69         /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  70         bool                    can_emulate_gicv2;
  71
  72         /* GIC system register CPU interface */
  73         struct static_key_false gicv3_cpuif;
  74
  75         u32                     ich_vtr_el2;
  76 };
  77
  78 extern struct vgic_global kvm_vgic_global_state;
  79
  80 #define VGIC_V2_MAX_LRS         (1 << 6)
  81 #define VGIC_V3_MAX_LRS         16
  82 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  83
  84 enum vgic_irq_config {
  85         VGIC_CONFIG_EDGE = 0,
  86         VGIC_CONFIG_LEVEL
  87 };
  88
  89 struct vgic_irq {
  90         spinlock_t irq_lock;            /* Protects the content of the struct */
  91         struct list_head lpi_list;      /* Used to link all LPIs together */
  92         struct list_head ap_list;
  93
  94         struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
  95                                          * SPIs and LPIs: The VCPU whose ap_list
  96                                          * this is queued on.
  97                                          */
  98
  99         struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
 100                                          * be sent to, as a result of the
 101                                          * targets reg (v2) or the
 102                                          * affinity reg (v3).
 103                                          */
 104
 105         u32 intid;                      /* Guest visible INTID */
 106         bool line_level;                /* Level only */
 107         bool pending_latch;             /* The pending latch state used to calculate
 108                                          * the pending state for both level
 109                                          * and edge triggered IRQs. */
 110         bool active;                    /* not used for LPIs */
 111         bool enabled;
 112         bool hw;                        /* Tied to HW IRQ */
 113         struct kref refcount;           /* Used for LPIs */
 114         u32 hwintid;                    /* HW INTID number */
 115         union {
 116                 u8 targets;                     /* GICv2 target VCPUs mask */
 117                 u32 mpidr;                      /* GICv3 target VCPU */
 118         };
 119         u8 source;                      /* GICv2 SGIs only */
 120         u8 priority;
 121         enum vgic_irq_config config;    /* Level or edge */
 122 };
 123
 124 struct vgic_register_region;
 125 struct vgic_its;
 126
 127 enum iodev_type {
 128         IODEV_CPUIF,
 129         IODEV_DIST,
 130         IODEV_REDIST,
 131         IODEV_ITS
 132 };
 133
 134 struct vgic_io_device {
 135         gpa_t base_addr;
 136         union {
 137                 struct kvm_vcpu *redist_vcpu;
 138                 struct vgic_its *its;
 139         };
 140         const struct vgic_register_region *regions;
 141         enum iodev_type iodev_type;
 142         int nr_regions;
 143         struct kvm_io_device dev;
 144 };
 145
 146 struct vgic_its {
 147         /* The base address of the ITS control register frame */
 148         gpa_t                   vgic_its_base;
 149
 150         bool                    enabled;
 151         bool                    initialized;
 152         struct vgic_io_device   iodev;
 153         struct kvm_device       *dev;
 154
 155         /* These registers correspond to GITS_BASER{0,1} */
 156         u64                     baser_device_table;
 157         u64                     baser_coll_table;
 158
 159         /* Protects the command queue */
 160         struct mutex            cmd_lock;
 161         u64                     cbaser;
 162         u32                     creadr;
 163         u32                     cwriter;
 164
 165         /* Protects the device and collection lists */
 166         struct mutex            its_lock;
 167         struct list_head        device_list;
 168         struct list_head        collection_list;
 169 };
 170
 171 struct vgic_state_iter;
 172
 173 struct vgic_dist {
 174         bool                    in_kernel;
 175         bool                    ready;
 176         bool                    initialized;
 177
 178         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 179         u32                     vgic_model;
 180
 181         /* Do injected MSIs require an additional device ID? */
 182         bool                    msis_require_devid;
 183
 184         int                     nr_spis;
 185
 186         /* TODO: Consider moving to global state */
 187         /* Virtual control interface mapping */
 188         void __iomem            *vctrl_base;
 189
 190         /* base addresses in guest physical address space: */
 191         gpa_t                   vgic_dist_base;         /* distributor */
 192         union {
 193                 /* either a GICv2 CPU interface */
 194                 gpa_t                   vgic_cpu_base;
 195                 /* or a number of GICv3 redistributor regions */
 196                 gpa_t                   vgic_redist_base;
 197         };
 198
 199         /* distributor enabled */
 200         bool                    enabled;
 201
 202         struct vgic_irq         *spis;
 203
 204         struct vgic_io_device   dist_iodev;
 205
 206         bool                    has_its;
 207
 208         /*
 209          * Contains the attributes and gpa of the LPI configuration table.
 210          * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 211          * one address across all redistributors.
 212          * GICv3 spec: 6.1.2 "LPI Configuration tables"
 213          */
 214         u64                     propbaser;
 215
 216         /* Protects the lpi_list and the count value below. */
 217         spinlock_t              lpi_list_lock;
 218         struct list_head        lpi_list_head;
 219         int                     lpi_list_count;
 220
 221         /* used by vgic-debug */
 222         struct vgic_state_iter *iter;
 223 };
 224
 225 struct vgic_v2_cpu_if {
 226         u32             vgic_hcr;
 227         u32             vgic_vmcr;
 228         u32             vgic_misr;      /* Saved only */
 229         u64             vgic_eisr;      /* Saved only */
 230         u64             vgic_elrsr;     /* Saved only */
 231         u32             vgic_apr;
 232         u32             vgic_lr[VGIC_V2_MAX_LRS];
 233 };
 234
 235 struct vgic_v3_cpu_if {
 236         u32             vgic_hcr;
 237         u32             vgic_vmcr;
 238         u32             vgic_sre;       /* Restored only, change ignored */
 239         u32             vgic_misr;      /* Saved only */
 240         u32             vgic_eisr;      /* Saved only */
 241         u32             vgic_elrsr;     /* Saved only */
 242         u32             vgic_ap0r[4];
 243         u32             vgic_ap1r[4];
 244         u64             vgic_lr[VGIC_V3_MAX_LRS];
 245 };
 246
 247 struct vgic_cpu {
 248         /* CPU vif control registers for world switch */
 249         union {
 250                 struct vgic_v2_cpu_if   vgic_v2;
 251                 struct vgic_v3_cpu_if   vgic_v3;
 252         };
 253
 254         unsigned int used_lrs;
 255         struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 256
 257         spinlock_t ap_list_lock;        /* Protects the ap_list */
 258
 259         /*
 260          * List of IRQs that this VCPU should consider because they are either
 261          * Active or Pending (hence the name; AP list), or because they recently
 262          * were one of the two and need to be migrated off this list to another
 263          * VCPU.
 264          */
 265         struct list_head ap_list_head;
 266
 267         u64 live_lrs;
 268
 269         /*
 270          * Members below are used with GICv3 emulation only and represent
 271          * parts of the redistributor.
 272          */
 273         struct vgic_io_device   rd_iodev;
 274         struct vgic_io_device   sgi_iodev;
 275
 276         /* Contains the attributes and gpa of the LPI pending tables. */
 277         u64 pendbaser;
 278
 279         bool lpis_enabled;
 280
 281         /* Cache guest priority bits */
 282         u32 num_pri_bits;
 283
 284         /* Cache guest interrupt ID bits */
 285         u32 num_id_bits;
 286 };
 287
 288 extern struct static_key_false vgic_v2_cpuif_trap;
 289
 290 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 291 void kvm_vgic_early_init(struct kvm *kvm);
 292 int kvm_vgic_create(struct kvm *kvm, u32 type);
 293 void kvm_vgic_destroy(struct kvm *kvm);
 294 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
 295 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 296 int kvm_vgic_map_resources(struct kvm *kvm);
 297 int kvm_vgic_hyp_init(void);
 298
 299 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 300                         bool level);
 301 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 302                                bool level);
 303 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
 304 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 305 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 306
 307 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 308
 309 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 310 #define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 311 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 312 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 313                         ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 314
 315 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 316 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 317 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 318
 319 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
 320
 321 /**
 322  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 323  *
 324  * The host's GIC naturally limits the maximum amount of VCPUs a guest
 325  * can use.
 326  */
 327 static inline int kvm_vgic_get_max_vcpus(void)
 328 {
 329         return kvm_vgic_global_state.max_gic_vcpus;
 330 }
 331
 332 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
 333
 334 /**
 335  * kvm_vgic_setup_default_irq_routing:
 336  * Setup a default flat gsi routing table mapping all SPIs
 337  */
 338 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
 339
 340 #endif /* __KVM_ARM_VGIC_H */