include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_H
  17 #define __KVM_ARM_VGIC_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/kvm.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/static_key.h>
  24 #include <linux/types.h>
  25 #include <kvm/iodev.h>
  26 #include <linux/list.h>
  27 #include <linux/jump_label.h>
  28
  29 #include <linux/irqchip/arm-gic-v4.h>
  30
  31 #define VGIC_V3_MAX_CPUS        255
  32 #define VGIC_V2_MAX_CPUS        8
  33 #define VGIC_NR_IRQS_LEGACY     256
  34 #define VGIC_NR_SGIS            16
  35 #define VGIC_NR_PPIS            16
  36 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  37 #define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  38 #define VGIC_MAX_SPI            1019
  39 #define VGIC_MAX_RESERVED       1023
  40 #define VGIC_MIN_LPI            8192
  41 #define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
  42
  43 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
  44 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
  45                          (irq) <= VGIC_MAX_SPI)
  46
  47 enum vgic_type {
  48         VGIC_V2,                /* Good ol' GICv2 */
  49         VGIC_V3,                /* New fancy GICv3 */
  50 };
  51
  52 /* same for all guests, as depending only on the _host's_ GIC model */
  53 struct vgic_global {
  54         /* type of the host GIC */
  55         enum vgic_type          type;
  56
  57         /* Physical address of vgic virtual cpu interface */
  58         phys_addr_t             vcpu_base;
  59
  60         /* GICV mapping */
  61         void __iomem            *vcpu_base_va;
  62
  63         /* virtual control interface mapping */
  64         void __iomem            *vctrl_base;
  65
  66         /* Number of implemented list registers */
  67         int                     nr_lr;
  68
  69         /* Maintenance IRQ number */
  70         unsigned int            maint_irq;
  71
  72         /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  73         int                     max_gic_vcpus;
  74
  75         /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  76         bool                    can_emulate_gicv2;
  77
  78         /* Hardware has GICv4? */
  79         bool                    has_gicv4;
  80
  81         /* GIC system register CPU interface */
  82         struct static_key_false gicv3_cpuif;
  83
  84         u32                     ich_vtr_el2;
  85 };
  86
  87 extern struct vgic_global kvm_vgic_global_state;
  88
  89 #define VGIC_V2_MAX_LRS         (1 << 6)
  90 #define VGIC_V3_MAX_LRS         16
  91 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  92
  93 enum vgic_irq_config {
  94         VGIC_CONFIG_EDGE = 0,
  95         VGIC_CONFIG_LEVEL
  96 };
  97
  98 struct vgic_irq {
  99         spinlock_t irq_lock;            /* Protects the content of the struct */
 100         struct list_head lpi_list;      /* Used to link all LPIs together */
 101         struct list_head ap_list;
 102
 103         struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
 104                                          * SPIs and LPIs: The VCPU whose ap_list
 105                                          * this is queued on.
 106                                          */
 107
 108         struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
 109                                          * be sent to, as a result of the
 110                                          * targets reg (v2) or the
 111                                          * affinity reg (v3).
 112                                          */
 113
 114         u32 intid;                      /* Guest visible INTID */
 115         bool line_level;                /* Level only */
 116         bool pending_latch;             /* The pending latch state used to calculate
 117                                          * the pending state for both level
 118                                          * and edge triggered IRQs. */
 119         bool active;                    /* not used for LPIs */
 120         bool enabled;
 121         bool hw;                        /* Tied to HW IRQ */
 122         struct kref refcount;           /* Used for LPIs */
 123         u32 hwintid;                    /* HW INTID number */
 124         unsigned int host_irq;          /* linux irq corresponding to hwintid */
 125         union {
 126                 u8 targets;                     /* GICv2 target VCPUs mask */
 127                 u32 mpidr;                      /* GICv3 target VCPU */
 128         };
 129         u8 source;                      /* GICv2 SGIs only */
 130         u8 priority;
 131         enum vgic_irq_config config;    /* Level or edge */
 132
 133         void *owner;                    /* Opaque pointer to reserve an interrupt
 134                                            for in-kernel devices. */
 135 };
 136
 137 struct vgic_register_region;
 138 struct vgic_its;
 139
 140 enum iodev_type {
 141         IODEV_CPUIF,
 142         IODEV_DIST,
 143         IODEV_REDIST,
 144         IODEV_ITS
 145 };
 146
 147 struct vgic_io_device {
 148         gpa_t base_addr;
 149         union {
 150                 struct kvm_vcpu *redist_vcpu;
 151                 struct vgic_its *its;
 152         };
 153         const struct vgic_register_region *regions;
 154         enum iodev_type iodev_type;
 155         int nr_regions;
 156         struct kvm_io_device dev;
 157 };
 158
 159 struct vgic_its {
 160         /* The base address of the ITS control register frame */
 161         gpa_t                   vgic_its_base;
 162
 163         bool                    enabled;
 164         struct vgic_io_device   iodev;
 165         struct kvm_device       *dev;
 166
 167         /* These registers correspond to GITS_BASER{0,1} */
 168         u64                     baser_device_table;
 169         u64                     baser_coll_table;
 170
 171         /* Protects the command queue */
 172         struct mutex            cmd_lock;
 173         u64                     cbaser;
 174         u32                     creadr;
 175         u32                     cwriter;
 176
 177         /* migration ABI revision in use */
 178         u32                     abi_rev;
 179
 180         /* Protects the device and collection lists */
 181         struct mutex            its_lock;
 182         struct list_head        device_list;
 183         struct list_head        collection_list;
 184 };
 185
 186 struct vgic_state_iter;
 187
 188 struct vgic_dist {
 189         bool                    in_kernel;
 190         bool                    ready;
 191         bool                    initialized;
 192
 193         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 194         u32                     vgic_model;
 195
 196         /* Do injected MSIs require an additional device ID? */
 197         bool                    msis_require_devid;
 198
 199         int                     nr_spis;
 200
 201         /* TODO: Consider moving to global state */
 202         /* Virtual control interface mapping */
 203         void __iomem            *vctrl_base;
 204
 205         /* base addresses in guest physical address space: */
 206         gpa_t                   vgic_dist_base;         /* distributor */
 207         union {
 208                 /* either a GICv2 CPU interface */
 209                 gpa_t                   vgic_cpu_base;
 210                 /* or a number of GICv3 redistributor regions */
 211                 struct {
 212                         gpa_t           vgic_redist_base;
 213                         gpa_t           vgic_redist_free_offset;
 214                 };
 215         };
 216
 217         /* distributor enabled */
 218         bool                    enabled;
 219
 220         struct vgic_irq         *spis;
 221
 222         struct vgic_io_device   dist_iodev;
 223
 224         bool                    has_its;
 225
 226         /*
 227          * Contains the attributes and gpa of the LPI configuration table.
 228          * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 229          * one address across all redistributors.
 230          * GICv3 spec: 6.1.2 "LPI Configuration tables"
 231          */
 232         u64                     propbaser;
 233
 234         /* Protects the lpi_list and the count value below. */
 235         raw_spinlock_t          lpi_list_lock;
 236         struct list_head        lpi_list_head;
 237         int                     lpi_list_count;
 238
 239         /* used by vgic-debug */
 240         struct vgic_state_iter *iter;
 241
 242         /*
 243          * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
 244          * array, the property table pointer as well as allocation
 245          * data. This essentially ties the Linux IRQ core and ITS
 246          * together, and avoids leaking KVM's data structures anywhere
 247          * else.
 248          */
 249         struct its_vm           its_vm;
 250 };
 251
 252 struct vgic_v2_cpu_if {
 253         u32             vgic_hcr;
 254         u32             vgic_vmcr;
 255         u64             vgic_elrsr;     /* Saved only */
 256         u32             vgic_apr;
 257         u32             vgic_lr[VGIC_V2_MAX_LRS];
 258 };
 259
 260 struct vgic_v3_cpu_if {
 261         u32             vgic_hcr;
 262         u32             vgic_vmcr;
 263         u32             vgic_sre;       /* Restored only, change ignored */
 264         u32             vgic_elrsr;     /* Saved only */
 265         u32             vgic_ap0r[4];
 266         u32             vgic_ap1r[4];
 267         u64             vgic_lr[VGIC_V3_MAX_LRS];
 268
 269         /*
 270          * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
 271          * pending table pointer, the its_vm pointer and a few other
 272          * HW specific things. As for the its_vm structure, this is
 273          * linking the Linux IRQ subsystem and the ITS together.
 274          */
 275         struct its_vpe  its_vpe;
 276 };
 277
 278 struct vgic_cpu {
 279         /* CPU vif control registers for world switch */
 280         union {
 281                 struct vgic_v2_cpu_if   vgic_v2;
 282                 struct vgic_v3_cpu_if   vgic_v3;
 283         };
 284
 285         unsigned int used_lrs;
 286         struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 287
 288         spinlock_t ap_list_lock;        /* Protects the ap_list */
 289
 290         /*
 291          * List of IRQs that this VCPU should consider because they are either
 292          * Active or Pending (hence the name; AP list), or because they recently
 293          * were one of the two and need to be migrated off this list to another
 294          * VCPU.
 295          */
 296         struct list_head ap_list_head;
 297
 298         /*
 299          * Members below are used with GICv3 emulation only and represent
 300          * parts of the redistributor.
 301          */
 302         struct vgic_io_device   rd_iodev;
 303         struct vgic_io_device   sgi_iodev;
 304
 305         /* Contains the attributes and gpa of the LPI pending tables. */
 306         u64 pendbaser;
 307
 308         bool lpis_enabled;
 309
 310         /* Cache guest priority bits */
 311         u32 num_pri_bits;
 312
 313         /* Cache guest interrupt ID bits */
 314         u32 num_id_bits;
 315 };
 316
 317 extern struct static_key_false vgic_v2_cpuif_trap;
 318 extern struct static_key_false vgic_v3_cpuif_trap;
 319
 320 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 321 void kvm_vgic_early_init(struct kvm *kvm);
 322 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
 323 int kvm_vgic_create(struct kvm *kvm, u32 type);
 324 void kvm_vgic_destroy(struct kvm *kvm);
 325 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
 326 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 327 int kvm_vgic_map_resources(struct kvm *kvm);
 328 int kvm_vgic_hyp_init(void);
 329 void kvm_vgic_init_cpu_hardware(void);
 330
 331 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 332                         bool level, void *owner);
 333 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
 334                           u32 vintid);
 335 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
 336 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
 337
 338 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 339
 340 void kvm_vgic_load(struct kvm_vcpu *vcpu);
 341 void kvm_vgic_put(struct kvm_vcpu *vcpu);
 342 void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu);
 343
 344 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 345 #define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 346 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 347 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 348                         ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 349
 350 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 351 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 352 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 353 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
 354
 355 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
 356
 357 /**
 358  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 359  *
 360  * The host's GIC naturally limits the maximum amount of VCPUs a guest
 361  * can use.
 362  */
 363 static inline int kvm_vgic_get_max_vcpus(void)
 364 {
 365         return kvm_vgic_global_state.max_gic_vcpus;
 366 }
 367
 368 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
 369
 370 /**
 371  * kvm_vgic_setup_default_irq_routing:
 372  * Setup a default flat gsi routing table mapping all SPIs
 373  */
 374 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
 375
 376 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
 377
 378 struct kvm_kernel_irq_routing_entry;
 379
 380 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
 381                                struct kvm_kernel_irq_routing_entry *irq_entry);
 382
 383 int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
 384                                  struct kvm_kernel_irq_routing_entry *irq_entry);
 385
 386 void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
 387 void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
 388
 389 #endif /* __KVM_ARM_VGIC_H */