include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_H
  17 #define __KVM_ARM_VGIC_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/kvm.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/static_key.h>
  24 #include <linux/types.h>
  25 #include <kvm/iodev.h>
  26 #include <linux/list.h>
  27 #include <linux/jump_label.h>
  28
  29 #define VGIC_V3_MAX_CPUS        255
  30 #define VGIC_V2_MAX_CPUS        8
  31 #define VGIC_NR_IRQS_LEGACY     256
  32 #define VGIC_NR_SGIS            16
  33 #define VGIC_NR_PPIS            16
  34 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  35 #define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  36 #define VGIC_MAX_SPI            1019
  37 #define VGIC_MAX_RESERVED       1023
  38 #define VGIC_MIN_LPI            8192
  39 #define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
  40
  41 enum vgic_type {
  42         VGIC_V2,                /* Good ol' GICv2 */
  43         VGIC_V3,                /* New fancy GICv3 */
  44 };
  45
  46 /* same for all guests, as depending only on the _host's_ GIC model */
  47 struct vgic_global {
  48         /* type of the host GIC */
  49         enum vgic_type          type;
  50
  51         /* Physical address of vgic virtual cpu interface */
  52         phys_addr_t             vcpu_base;
  53
  54         /* GICV mapping */
  55         void __iomem            *vcpu_base_va;
  56
  57         /* virtual control interface mapping */
  58         void __iomem            *vctrl_base;
  59
  60         /* Number of implemented list registers */
  61         int                     nr_lr;
  62
  63         /* Maintenance IRQ number */
  64         unsigned int            maint_irq;
  65
  66         /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  67         int                     max_gic_vcpus;
  68
  69         /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  70         bool                    can_emulate_gicv2;
  71
  72         /* GIC system register CPU interface */
  73         struct static_key_false gicv3_cpuif;
  74
  75         u32                     ich_vtr_el2;
  76 };
  77
  78 extern struct vgic_global kvm_vgic_global_state;
  79
  80 #define VGIC_V2_MAX_LRS         (1 << 6)
  81 #define VGIC_V3_MAX_LRS         16
  82 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  83
  84 enum vgic_irq_config {
  85         VGIC_CONFIG_EDGE = 0,
  86         VGIC_CONFIG_LEVEL
  87 };
  88
  89 struct vgic_irq {
  90         spinlock_t irq_lock;            /* Protects the content of the struct */
  91         struct list_head lpi_list;      /* Used to link all LPIs together */
  92         struct list_head ap_list;
  93
  94         struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
  95                                          * SPIs and LPIs: The VCPU whose ap_list
  96                                          * this is queued on.
  97                                          */
  98
  99         struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
 100                                          * be sent to, as a result of the
 101                                          * targets reg (v2) or the
 102                                          * affinity reg (v3).
 103                                          */
 104
 105         u32 intid;                      /* Guest visible INTID */
 106         bool line_level;                /* Level only */
 107         bool pending_latch;             /* The pending latch state used to calculate
 108                                          * the pending state for both level
 109                                          * and edge triggered IRQs. */
 110         bool active;                    /* not used for LPIs */
 111         bool enabled;
 112         bool hw;                        /* Tied to HW IRQ */
 113         struct kref refcount;           /* Used for LPIs */
 114         u32 hwintid;                    /* HW INTID number */
 115         union {
 116                 u8 targets;                     /* GICv2 target VCPUs mask */
 117                 u32 mpidr;                      /* GICv3 target VCPU */
 118         };
 119         u8 source;                      /* GICv2 SGIs only */
 120         u8 priority;
 121         enum vgic_irq_config config;    /* Level or edge */
 122 };
 123
 124 struct vgic_register_region;
 125 struct vgic_its;
 126
 127 enum iodev_type {
 128         IODEV_CPUIF,
 129         IODEV_DIST,
 130         IODEV_REDIST,
 131         IODEV_ITS
 132 };
 133
 134 struct vgic_io_device {
 135         gpa_t base_addr;
 136         union {
 137                 struct kvm_vcpu *redist_vcpu;
 138                 struct vgic_its *its;
 139         };
 140         const struct vgic_register_region *regions;
 141         enum iodev_type iodev_type;
 142         int nr_regions;
 143         struct kvm_io_device dev;
 144 };
 145
 146 struct vgic_its {
 147         /* The base address of the ITS control register frame */
 148         gpa_t                   vgic_its_base;
 149
 150         bool                    enabled;
 151         struct vgic_io_device   iodev;
 152         struct kvm_device       *dev;
 153
 154         /* These registers correspond to GITS_BASER{0,1} */
 155         u64                     baser_device_table;
 156         u64                     baser_coll_table;
 157
 158         /* Protects the command queue */
 159         struct mutex            cmd_lock;
 160         u64                     cbaser;
 161         u32                     creadr;
 162         u32                     cwriter;
 163
 164         /* migration ABI revision in use */
 165         u32                     abi_rev;
 166
 167         /* Protects the device and collection lists */
 168         struct mutex            its_lock;
 169         struct list_head        device_list;
 170         struct list_head        collection_list;
 171 };
 172
 173 struct vgic_state_iter;
 174
 175 struct vgic_dist {
 176         bool                    in_kernel;
 177         bool                    ready;
 178         bool                    initialized;
 179
 180         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 181         u32                     vgic_model;
 182
 183         /* Do injected MSIs require an additional device ID? */
 184         bool                    msis_require_devid;
 185
 186         int                     nr_spis;
 187
 188         /* TODO: Consider moving to global state */
 189         /* Virtual control interface mapping */
 190         void __iomem            *vctrl_base;
 191
 192         /* base addresses in guest physical address space: */
 193         gpa_t                   vgic_dist_base;         /* distributor */
 194         union {
 195                 /* either a GICv2 CPU interface */
 196                 gpa_t                   vgic_cpu_base;
 197                 /* or a number of GICv3 redistributor regions */
 198                 struct {
 199                         gpa_t           vgic_redist_base;
 200                         gpa_t           vgic_redist_free_offset;
 201                 };
 202         };
 203
 204         /* distributor enabled */
 205         bool                    enabled;
 206
 207         struct vgic_irq         *spis;
 208
 209         struct vgic_io_device   dist_iodev;
 210
 211         bool                    has_its;
 212
 213         /*
 214          * Contains the attributes and gpa of the LPI configuration table.
 215          * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 216          * one address across all redistributors.
 217          * GICv3 spec: 6.1.2 "LPI Configuration tables"
 218          */
 219         u64                     propbaser;
 220
 221         /* Protects the lpi_list and the count value below. */
 222         spinlock_t              lpi_list_lock;
 223         struct list_head        lpi_list_head;
 224         int                     lpi_list_count;
 225
 226         /* used by vgic-debug */
 227         struct vgic_state_iter *iter;
 228 };
 229
 230 struct vgic_v2_cpu_if {
 231         u32             vgic_hcr;
 232         u32             vgic_vmcr;
 233         u64             vgic_elrsr;     /* Saved only */
 234         u32             vgic_apr;
 235         u32             vgic_lr[VGIC_V2_MAX_LRS];
 236 };
 237
 238 struct vgic_v3_cpu_if {
 239         u32             vgic_hcr;
 240         u32             vgic_vmcr;
 241         u32             vgic_sre;       /* Restored only, change ignored */
 242         u32             vgic_elrsr;     /* Saved only */
 243         u32             vgic_ap0r[4];
 244         u32             vgic_ap1r[4];
 245         u64             vgic_lr[VGIC_V3_MAX_LRS];
 246 };
 247
 248 struct vgic_cpu {
 249         /* CPU vif control registers for world switch */
 250         union {
 251                 struct vgic_v2_cpu_if   vgic_v2;
 252                 struct vgic_v3_cpu_if   vgic_v3;
 253         };
 254
 255         unsigned int used_lrs;
 256         struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 257
 258         spinlock_t ap_list_lock;        /* Protects the ap_list */
 259
 260         /*
 261          * List of IRQs that this VCPU should consider because they are either
 262          * Active or Pending (hence the name; AP list), or because they recently
 263          * were one of the two and need to be migrated off this list to another
 264          * VCPU.
 265          */
 266         struct list_head ap_list_head;
 267
 268         /*
 269          * Members below are used with GICv3 emulation only and represent
 270          * parts of the redistributor.
 271          */
 272         struct vgic_io_device   rd_iodev;
 273         struct vgic_io_device   sgi_iodev;
 274
 275         /* Contains the attributes and gpa of the LPI pending tables. */
 276         u64 pendbaser;
 277
 278         bool lpis_enabled;
 279
 280         /* Cache guest priority bits */
 281         u32 num_pri_bits;
 282
 283         /* Cache guest interrupt ID bits */
 284         u32 num_id_bits;
 285 };
 286
 287 extern struct static_key_false vgic_v2_cpuif_trap;
 288
 289 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 290 void kvm_vgic_early_init(struct kvm *kvm);
 291 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
 292 int kvm_vgic_create(struct kvm *kvm, u32 type);
 293 void kvm_vgic_destroy(struct kvm *kvm);
 294 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
 295 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 296 int kvm_vgic_map_resources(struct kvm *kvm);
 297 int kvm_vgic_hyp_init(void);
 298 void kvm_vgic_init_cpu_hardware(void);
 299
 300 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 301                         bool level);
 302 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 303                                bool level);
 304 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
 305 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 306 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 307
 308 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 309
 310 void kvm_vgic_load(struct kvm_vcpu *vcpu);
 311 void kvm_vgic_put(struct kvm_vcpu *vcpu);
 312
 313 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 314 #define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 315 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 316 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 317                         ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 318
 319 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 320 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 321 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 322
 323 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
 324
 325 /**
 326  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 327  *
 328  * The host's GIC naturally limits the maximum amount of VCPUs a guest
 329  * can use.
 330  */
 331 static inline int kvm_vgic_get_max_vcpus(void)
 332 {
 333         return kvm_vgic_global_state.max_gic_vcpus;
 334 }
 335
 336 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
 337
 338 /**
 339  * kvm_vgic_setup_default_irq_routing:
 340  * Setup a default flat gsi routing table mapping all SPIs
 341  */
 342 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
 343
 344 #endif /* __KVM_ARM_VGIC_H */